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參數(shù)資料
| 型號(hào)： | KSZ8841-16MVLI |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 54/105頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MAC CTRLR 8/16BIT 128-LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 控制器類型： | 以太網(wǎng)控制器，MAC |
| 接口： | 總線 |
| 電源電壓： | 3.1 V ~ 3.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 1081 (CN2011-ZH PDF) |
| 配用： | 576-1632-ND - BOARD EVALUATION KSZ8841-16MVL |
| 其它名稱： | 576-2114 KSZ8841-16MVLI-ND |
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Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
52
M9999-102207-1.6
Register Map: MAC and PHY
Do not write to bit values or to registers defined as Reserved. Manipulating reserved bits or registers causes
unpredictable and often fatal results. If the user wants to write to these reserved bits, the user has to read back these
reserved bits (RO or RW) first, then “OR” with the read value of the reserved bits and write back to these reserved bits.
Bit Type Definition
RO = Read only.
RW = Read/Write.
W1C = Write 1 to Clear (writing a one to this bit clears it).
Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks)
The bank select register is used to select or to switch between different sets of register banks for I/O access.
There are a total of 64 banks available to select, including the built-in switch engine registers.
Bit
Default Value
R/W
Description
15-6
0x000
RO
Reserved
5-0
0x00
R/W
BSA Bank Select Address Bits
BSA bits select the I/O register bank in use.
This register is always accessible regardless of the register bank currently selected.
Notes:
The bank select register can be accessed as a doubleword (32-bit) at offset 0xC, as a word
(16-bit) at offset 0xE, or as a byte (8-bit) at offset 0xE.
A doubleword write to offset 0xC writes to the BANK Select Register but does not write to
registers 0xC and 0xD; it only writes to register 0xE.
Bank 0 Base Address Register (0x00): BAR
This register holds the base address for decoding a device access. Its value is loaded from the external EEPROM (0x0H)
upon a power-on reset if the EEPROM Enable (EEEN) pin is tied to High. Its value can also be modified after reset.
Writing to this register does not store the value into the EEPROM. When the EEEN pin is tied to Low, the default base
address is 0x300.
Bit
Default Value
R/W
Description
15-8
0x03 if EEEN
is Low or, the
value from
EEPROM if
EEEN is High
RW
BARH Base Address High
These bits are compared against the address on the bus ADDR[15:8] to determine the
BASE for the KSZ8841M registers.
7-5
0x00 if EEEN
is Low or, the
value from
EEPROM if
EEEN is High
RW
BARL Base Address Low
These bits are compared against the address on the bus ADDR[7:5] to determine the BASE
for the KSZ8841M registers.
4-0
0x00
RO
Reserved
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| KSZ8841-16MVLI TR | 功能描述:以太網(wǎng) IC Single Ethernet Port + Generic (8, 16-bit) bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8841-32MQL | 功能描述:以太網(wǎng) IC Single Ethernet Port + Generic (32-bit) bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8841-32MVL | 功能描述:以太網(wǎng) IC Single Ethernet Port + Generic (32-bit) bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8841-32MVLI | 功能描述:以太網(wǎng) IC Single Ethernet Port + Generic (32-bit) bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ8841P | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:Ethernet MAC Controller with PCI Interface |
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