參數(shù)資料
型號: KSZ8841-16MVLI
廠商: Micrel Inc
文件頁數(shù): 96/105頁
文件大?。?/td> 0K
描述: IC MAC CTRLR 8/16BIT 128-LQFP
標(biāo)準(zhǔn)包裝: 90
控制器類型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x14)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-1632-ND - BOARD EVALUATION KSZ8841-16MVL
其它名稱: 576-2114
KSZ8841-16MVLI-ND
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
90
M9999-102207-1.6
Asynchronous Timing using Address Strobe (ADSN)
t2
t7
t5
t4
t3
t1
t6
t8
valid
Addr, AEN, BExN
ADSN
Read Data
RDN, WRN
Write Data
ARDY
(Read Cycle)
ARDY
(Write Cycle)
t9
t10
t11
Figure 14. Asynchronous Cycle – Using ADSN
Symbol
Parameter
Min
Typ
Max
Unit
t1
A1-A15, AEN, BExN[3:0] valid to RDN, WRN active
0
ns
t2
Read data valid to ARDY rising
0.8
ns
t3
Read data hold to RDN inactive
4
ns
t4
Write data setup to WRN inactive
4
ns
t5
Write data hold after WRN inactive
2
ns
t6
A1-A15, AEN, nBE[3:0] setup to ADSN rising
4
ns
t7
Read active to ARDY Low
8
ns
t8
A1-A15, AEN, BExN[3:0] hold after ADSN rising
2
ns
t9
Write inactive to ARDY Low
8
ns
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register and 40ns to
read QMU data register in turbo mode) (Note2)
0
40
ns
t10
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register and 80ns to
read QMU data register in normal mode)
0
80
ns
t11
ARDY low (wait time) in write cycle (Note1)
(It is 0ns to write bank select register)
(It is 36ns to write QMU data register)
0
50
ns
Table 17. Asynchronous Cycle using ADSN Timing Parameters
Notes:
1.
When CPU finished current Read or Write operation, it can do next Read or Write operation even the ARDY is low. During Read or Write
operation if the ADRY is low, the CPU has to keep the RDN/WRN low until the ARDY returns to high.
2.
In order to speed up the ARDY low time to 40ns, user has to use the turbo software driver which is only supported in the A6 device.
Please refer to the “KSZ88xx Programmer's Guide” for detail.
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