參數(shù)資料
型號(hào)： KSZ8841-PMQLI
廠商： Micrel Inc
文件頁數(shù)： 19/74頁
文件大小： 0K
描述： IC MAC CTRLR 32BIT PCI 128-PQFP
標(biāo)準(zhǔn)包裝： 66
控制器類型： 以太網(wǎng)控制器，MAC
接口： 總線
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁面： 1080 (CN2011-ZH PDF)
配用： 576-1633-ND - BOARD EVALUATION KSZ8841-PMQL
其它名稱： 576-2118
KSZ8841-PMQLI-ND
Micrel, Inc.
KSZ8841-PMQL
October 2007
26
M9999-100407-1.5
The following table shows the RDES1 register bit fields.
Bit
Description
31 - 26
Reserved
25
RER Receive End of Ring
When set, indicates that the descriptor list reached its final descriptor. The KSZ8841-PMQL
returns to the base address of the list, thus creating a descriptor ring.
24 - 12
Reserved
10 - 0
RBS Receive Buffer Size
Indicates the size, in bytes, of the receive data buffer. If the field is 0, the KSZ8841-PMQL
ignores this buffer and moves to the next descriptor.
The buffer size must be a multiple of 4.
The following table shows the RDES2 register bit fields.
Bit
Description
31 - 0
Buffer Address
Indicates the physical memory address of the buffer.
The buffer address must be Word aligned.
The following table shows the RDES3 register bit fields.
Bit
Description
31 - 0
Next Descriptor Address
Indicates the physical memory address of the next descriptor in the descriptor ring.
The buffer address must be Word aligned.
Transmit Descriptors (TDES0-TDES3)
Transmit descriptors must be Word aligned. Each descriptor provides one frame buffer, one byte count field, and
control and status bits.
The following table shows the TDES0 register bit fields.
Bit
Description
31
OWN Own Bit
When set, indicates that the descriptor is owned by the KSZ8841-PMQL. When cleared,
indicates that the descriptor is owned by the host. The KSZ8841-PMQL clears this bit either
when it completes the frame transmission or when the buffer allocated in the descriptor is
empty.
The ownership bit of the first descriptor of the frame should be set after all subsequent
descriptors belonging to the same frame have been set. This avoids a possible race
condition between the KSZ8841-PMQL fetching a descriptor and the driver setting an
ownership bit.
30 - 0
Reserved
The following table shows the TDES1 register bit fields.
Bit
Description
31
IC Interrupt on Completion
When set, the KSZ8841-PMQL sets transmit interrupt after the present frame has been
transmitted. It is valid only when last segment is set.
30
FS First Segment
When set, indicates that the buffer contains the first segment of a frame.
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