參數(shù)資料
型號： KSZ8841-PMQLI
廠商： Micrel Inc
文件頁數(shù)： 30/74頁
文件大?。?/td> 0K
描述： IC MAC CTRLR 32BIT PCI 128-PQFP
標(biāo)準(zhǔn)包裝： 66
控制器類型： 以太網(wǎng)控制器，MAC
接口： 總線
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁面： 1080 (CN2011-ZH PDF)
配用： 576-1633-ND - BOARD EVALUATION KSZ8841-PMQL
其它名稱： 576-2118
KSZ8841-PMQLI-ND
Micrel, Inc.
KSZ8841-PMQL
October 2007
36
M9999-100407-1.5
The following table shows the access rules of the register.
Category
Description
bit 15
Read/Write 1 Clear (RW1C)
bit 8
Read/Write (RW)
bit 3
Read Only (RO)
bit 1 – 0
Read Write (RW)
PCI Control & Status Registers
The PCI CSR registers are all 32 bit in Little Endian format. For PCI register Read cycle, the KSZ8841-PMQL allows
any different combination of CBEN. For PCI register bus cycles, only byte, word(16-bit), or Dword(32-bit) accesses are
allowed. Any other combinations are illegal, and will be target aborted.
All other registers not included below are reserved.
MAC DMA Transmit Control Register (MDTXC Offset 0x0000)
The MAC DMA transmit control register establishes the transmit operating modes and commands for the port. This
register should be one of the last CSRs to be written as part of the transmit initialization.
The following table shows the register bit fields.
Bit
Default
Read/
Write
Description
31-30
-
RO
Reserved
29 - 24
0x00
RW
MTBS DMA Transmit Burst Size
This field indicates the maximum number of words to be transferred in one
DMA transaction. If reset, the MAC DMA burst size is limited only by the
amount of data stored in the transmit buffer before issuing a bus request.
The MTBS can be programmed with permissible values 0,1, 2, 4, 8, 16, or
32.
After reset, the MTBS default is 0, i.e. unlimited.
23 - 19
0x00
RO
Reserved
18
0
RW
MTUCG MAC Transmit UDP Checksum Generate
When set, the KSZ8841-PMQL will generate correct UDP checksum for
outgoing UDP/IP frames at port.
When this bit is set, ADD CRC should also turn on.
17
0
RW
MTTCG MAC Transmit TCP Checksum Generate
When set, the KSZ8841-PMQL will generate correct TCP checksum for
outgoing TCP/IP frames at port.
When this bit is set, ADD CRC should also turn on.
16
0
RW
MTICG MAC Transmit IP Checksum Generate
When set, the KSZ8841-PMQL will generate correct IP checksum for
outgoing IP frames at port.
When this bit is set, ADD CRC should also turn on.
15 - 10
0x00
RO
Reserved
9
0
RW
MTFCE MAC Transmit Flow Control Enable
When this bit is set and the KSZ8841-PMQL is in Full Duplex mode, flow
control is enabled and the KSZ8841-PMQL will transmit a PAUSE frame
when the Receive Buffer capacity has reached a level that may cause the
buffer to overflow.
When this bit is set and the KSZ8841-PMQL is in Half Duplex mode, back-
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