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參數(shù)資料
| 型號： | KSZ8841-PMQLI |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 35/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MAC CTRLR 32BIT PCI 128-PQFP |
| 標準包裝： | 66 |
| 控制器類型： | 以太網(wǎng)控制器，MAC |
| 接口： | 總線 |
| 電源電壓： | 3.1 V ~ 3.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應商設備封裝： | 128-PQFP（14x20） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 1080 (CN2011-ZH PDF) |
| 配用： | 576-1633-ND - BOARD EVALUATION KSZ8841-PMQL |
| 其它名稱： | 576-2118 KSZ8841-PMQLI-ND |
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Micrel, Inc.
KSZ8841-PMQL
October 2007
40
M9999-100407-1.5
MAC Multicast Table 1 Register (MTR1 Offset 0x0024)
The 64 bit multicast table is used for group address filtering. The value is defined as the six most significant bits of the
CRC of the DA. The two most significant bits select the register to be used, while the other determines the bit within the
register.
Bit
Default
Read/
Write
Description
31-0
0x00000000
RW
MTR0 Multicast Table 1
When appropriate bit is set, the packet received with DA matches the
CRC hashing function is received without being filtered.
Note: when receive all (RXRA) or receive multicast (RXRM) bit is set in
the RXCR then all multicast addresses are received regardless of the
multicast table value.
Interrupt Enable Register (INTEN Offset 0x0028)
This register enables the interrupts from the internal or external sources.
The following table shows the register bit fields.
Bit
Default
Read/
Write
Description
31
0
RW
DMLCIE DMA MAC Link Changed Interrupt Enable
When this bit is set, the DMA MAC Link Changed Interrupt is enabled.
When this bit is reset, the DMA MAC Link Changed Interrupt is
disabled.
30
0
RW
DMTIE DMA MAC Transmit Interrupt Enable
When this bit is set, the DMA MAC Transmit Interrupt is enabled.
When this bit is reset, the DMA MAC Transmit Interrupt is disabled.
29
0
RW
DMRIE DMA MAC Receive Interrupt Enable
When this bit is set, the DMA MAC Receive Interrupt is enabled.
When this bit is reset, the DMA MAC Receive Interrupt is disabled.
28
0
RW
DMTBUIE DMA MAC Transmit Buffer Unavailable Interrupt Enable
When this bit is set, the DMA MAC Transmit Buffer Unavailable
Interrupt is enabled.
When this bit is reset, the DMA MAC Transmit Buffer Unavailable
Interrupt is disabled.
27
0
RW
DMRBUIE DMA MAC Receive Buffer Unavailable Interrupt Enable
When this bit is set, the DMA MAC Receive Buffer Unavailable Interrupt
is enabled.
When this bit is reset, the DMA MAC Receive Buffer Unavailable
Interrupt is disabled.
26
0
RW
DMTPSIE DMA MAC Transmit Process Stopped Interrupt Enable
When this bit is set, the DMA MAC Transmit Process Stopped Interrupt
is enabled.
When this bit is reset, the DMA MAC Transmit Process Stopped
Interrupt is disabled.
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