參數(shù)資料
型號(hào)： KSZ8841-PMQLI
廠商： Micrel Inc
文件頁(yè)數(shù)： 31/74頁(yè)
文件大?。?/td> 0K
描述： IC MAC CTRLR 32BIT PCI 128-PQFP
標(biāo)準(zhǔn)包裝： 66
控制器類型： 以太網(wǎng)控制器，MAC
接口： 總線
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 1080 (CN2011-ZH PDF)
配用： 576-1633-ND - BOARD EVALUATION KSZ8841-PMQL
其它名稱： 576-2118
KSZ8841-PMQLI-ND
Micrel, Inc.
KSZ8841-PMQL
October 2007
37
M9999-100407-1.5
Bit
Default
Read/
Write
Description
pressure flow control is enabled. When this bit is cleared, no transmit flow
control is enabled.
8 - 3
0x0
RO
Reserved
2
0
RW
MTEP MAC DMA Transmit Enable Padding
When set, the KSZ8841-PMQL automatically adds a padding field to a
packet shorter than 64 bytes.
Note: Setting this bit automatically enables Add CRC feature.
1
0
RW
MTAC MAC DMA Transmit Add CRC
When set, the KSZ8841-PMQL appends the CRC to the end of the
transmission frame.
0
RW
MTE MAC DMA TX Enable
When the bit is set, the MDMA TX block is enabled and placed in a running
state. When reset, the transmission process is placed in the stopped state
after completing the transmission of the current frame. The stop
transmission command is effective only when the transmission process is in
the running state.
MAC DMA Receive Control Register (MDRXC Offset 0x0004)
The MAC DMA receive control register establishes the receive operating modes and commands for the port. This
register should be one of the last CSRs to be written as part of the receive initialization.
The following table shows the register bit fields.
Bit
Default
Read/
Write
Description
31 - 30
00
RO
Reserved
29 - 24
0x00
RW
MRBS DMA Receive Burst Size
This field indicates the maximum number of words to be transferred in one
DMA transaction. If reset, the MAC DMA burst size is limited only by the
amount of data stored in the receive buffer before issuing a bus request.
The MRBS can be programmed with permissible values 0,1, 2, 4, 8, 16, or
32.
After reset, the MRBS default is 0, i.e. unlimited.
23 - 20
0x0
RO
Reserved
19
0
RW
IP Header Alignment Enable
1 = Enable alignment of IP header to dWord address. Layer 2 header will
not be dWord aligned anymore. Please look at RX descriptor 0 for the Layer
2 header address shift.
0 = IP Header alignment disabled.
18
0
RW
MRUCC MAC Receive UDP Checksum Check
When set, the KSZ8841-PMQL will check for correct UDP checksum for
incoming UDP/IP frames at port. Packets received with incorrect UDP
checksum will be discarded.
17
0
RW
MRTCG MAC Receive TCP Checksum Check
When set, the KSZ8841-PMQL will check for correct TCP checksum for
incoming TCP/IP frames at port. Packets received with incorrect TCP
checksum will be discarded.
16
0
RW
MRICG MAC Receive IP Checksum Check
When set, the KSZ8841-PMQL will check for correct IP checksum for
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