參數(shù)資料
型號(hào): KSZ8842-16MBLI TR
廠商: Micrel Inc
文件頁數(shù): 11/141頁
文件大?。?/td> 0K
描述: IC ETHERNET SW 2PORT 100LFBGA
標(biāo)準(zhǔn)包裝: 1,000
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LBGA
供應(yīng)商設(shè)備封裝: 100-LFBGA
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
108
M9999-102207-1.9
Bit
Default
R/W
Description
Bit is same as:
3
1
RW
Advertised 100BT full-duplex capability.
1 = advertise 100BT full-duplex capability.
0 = suppress 100BT full-duplex capability from
transmission to link partner.
Bank 45 0x08 bit 8
2
1
RW
Advertised 100BT half-duplex capability.
1 = advertise 100BT half-duplex capability.
0 = suppress 100BT half-duplex capability from
transmission to link partner.
Bank 45 0x08 bit 7
1
RW
Advertised 10BT full-duplex capability.
1 = advertise 10BT full-duplex capability.
0 = suppress 10BT full-duplex capability from
transmission to link partner.
Bank 45 0x08 bit 6
0
1
RW
Advertised 10BT half-duplex capability.
1 = advertise 10BT half-duplex capability.
0 = suppress 10BT half-duplex capability from
transmission to link partner.
Bank 45 0x08 bit 5
Bank 49 Port 1 Status Register (0x04): P1SR
This register contains the global per port status for the switch function.
Bit
Default
R/W
Description
Bit is same as:
15
1
RW
HP_mdix
1 = HP Auto MDI-X mode.
0 = Micrel Auto MDI-X mode.
Bank 45 0x00 bit 5
14
0
RO
Reserved
13
0
RO
Polarity Reverse
1 = polarity is reversed.
0 = polarity is not reversed.
Bank 47 0x02 bit 5
12
0
RO
Receive Flow Control Enable
1 = receive flow control feature is active.
0 = receive flow control feature is inactive.
11
0
RO
Transmit Flow Control Enable
1 = transmit flow control feature is active.
0 = transmit flow control feature is inactive.
10
0
RO
Operation Speed
1 = link speed is 100Mbps.
0 = link speed is 10Mbps.
9
0
RO
Operation Duplex
1 = link duplex is full.
0 = link duplex is half.
8
0
RO
Reserved
Bank 45 0x02 bit 4
7
0
RO
MDI-X status
1 = MDI.
0 = MDI-X.
Bank 47 0x02 bit 4
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