參數資料
型號: KSZ8842-16MBLI TR
廠商: Micrel Inc
文件頁數: 22/141頁
文件大?。?/td> 0K
描述: IC ETHERNET SW 2PORT 100LFBGA
標準包裝: 1,000
控制器類型: 以太網開關控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LBGA
供應商設備封裝: 100-LFBGA
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
118
M9999-102207-1.9
Examples:
1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E)
Write to reg. IACR with 0x1c0e (set indirect address and trigger a read MIB counters operation)
Then
Read reg. IADR5 (MIB counter value 31-16) // If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
Read reg. IADR4 (MIB counter value 15-0)
2. MIB Counter Read (read port 2 “Rx64Octets” counter at indirect address offset 0x2E)
Write to reg. IACR with 0x1c2e (set indirect address and trigger a read MIB counters operation)
Then
Read reg. IADR5 (MIB counter value 31-16) // If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (reread) from this register
Read reg. IADR4 (MIB counter value 15-0)
3. MIB Counter Read (read “Port1 TX Drop Packets” counter at indirect address offset 0x100)
Write to reg. IACR with 0x1d00 (set indirect address and trigger a read MIB counters operation)
Then
Read reg. IADR4 (MIB counter value 15-0)
Additional MIB Information
Per Port MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read.
All Ports Dropped Packet MIB counters are not cleared after they are accessed. The application needs to keep track of
overflow and valid conditions on these counters.
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參數描述
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