參數(shù)資料
型號： KSZ8842-16MBLI TR
廠商： Micrel Inc
文件頁數(shù)： 79/141頁
文件大?。?/td> 0K
描述： IC ETHERNET SW 2PORT 100LFBGA
標準包裝： 1,000
控制器類型： 以太網開關控制器
接口： PCI
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LBGA
供應商設備封裝： 100-LFBGA
包裝： 帶卷 (TR)
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
42
M9999-102207-1.9
Bit
Description
15
TXIC Transmit Interrupt on Completion
When bit is set, the KSZ8842M sets the transmit interrupt after the present frame has been
transmitted.
14-10
Reserved
9-8
TXDPN Transmit Destination Port Number
When bit is set, this field indicates the destination port(s) where the packet is forwarded
from host system. Set bit 8 to indicate that port 1 is the destination port. Set bit 9 to
indicate that port 2 is the destination port.
Setting all ports to 1 causes the switch engine to broadcast the packet to both ports.
Setting all bits to 0 has no effect. The internal switch engine forwards the packets
according to the switching algorithm in its MAC lookup table.
7-6
Reserved
5-0
TXFID Transmit Frame ID
This field specifies the frame ID that is used to identify the frame and its associated status
information in the transmit status register TXSR[5:0].
Table 4. Transmit Control Word Bit Fields
The transmit Byte Count specifies the total number of bytes to be transmitted from the TXQ. Its format is given in Table 5.
Bit
Description
15-11
Reserved
10-0
TXBC Transmit Byte Count
Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer
memory for better utilization of the packet memory.
Note: The hardware behavior is unknown if an incorrect byte count information is written to
this field. Writing a 0 value to this field is not permitted.
Table 5. Transmit Byte Count Format
The data area contains six bytes of Destination Address (DA) followed by six bytes of Source Address (SA), followed by a
variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
KSZ8842M does not insert its own source address. The 802.3 Frame Length word (Frame Type in Ethernet) is not
interpreted by the KSZ8842M. It is treated transparently as data for transmit operations.
Receive Queue (RXQ) Frame Format
The frame format for the receive queue is shown in Table 6. The first word contains the status information for the frame
received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The
packet data area holds the frame itself. It may or may not include the CRC checksum depending upon whether hardware
CRC stripping is enabled.
Packet Memory
Address Offset
Bit 15
Bit 0
2
nd Byte
1
st Byte
0
Status Word
2
Byte Count
4 - up
Packet Data
(maximum size is 1916)
Table 6. Receive Queue Frame Format
For receive, the packet receive status always reflects the receive status of the packet received in the current RX packet
memory (see Table 7). The RXSR register indicates the status of the current received frame.
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