參數(shù)資料
型號： KSZ8842-16MBLI TR
廠商： Micrel Inc
文件頁數(shù)： 21/141頁
文件大?。?/td> 0K
描述： IC ETHERNET SW 2PORT 100LFBGA
標準包裝： 1,000
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： PCI
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LBGA
供應(yīng)商設(shè)備封裝： 100-LFBGA
包裝： 帶卷 (TR)
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
117
M9999-102207-1.9
Offset
Counter Name
Description
0x13
Rx1024to1522Octets
Total Rx packets (bad packets included) that are between 1024 and 1522 octets in
length (upper limit depends on max packet size setting)
0x14
TxLoPriorityByte
Tx lo-priority good octet count, including PAUSE packets
0x15
TxHiPriorityByte
Tx hi-priority good octet count, including PAUSE packets
0x16
TxLateCollision
The number of times a collision is detected later than 512 bit-times into the Tx of a
packet
0x17
TxPausePkts
Number of PAUSE frames transmitted by a port
0x18
TxBroadcastPkts
Tx good broadcast packets (not including error broadcast or valid multicast packets)
0x19
TxMulticastPkts
Tx good multicast packets (not including error multicast packets or valid broadcast
packets)
0x1A
TxUnicastPkts
Tx good unicast packets
0x1B
TxDeferred
Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium
0x1C
TxTotalCollision
Tx total collision, half duplex only
0x1D
TxExcessiveCollision
A count of frames for which Tx fails due to excessive collisions
0x1E
TxSingleCollision
Successfully Tx frames on a port for which Tx is inhibited by exactly one collision
0x1F
TxMultipleCollision
Successfully Tx frames on a port for which Tx is inhibited by more than one collision
Table 15. Port 1 MIB Counters Indirect Memory Offset
Format of “All Ports Dropped Packet” MIB Counters
Bit
Default
R/W
Description
30-16
-
N/A
Reserved
15-0
0x0000
RO
Counter Value
Table 16. “All Ports Dropped Packet” MIB Counters Format
Note: “All Ports Dropped Packet” MIB Counters do not indicate overflow or validity; therefore, the application must keep track of
overflow and valid conditions.
“All Ports Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters
are shown in Table 17.
Offset
Counter Name
Description
0x100
Port1 TX Drop Packets
TX packets dropped due to lack of resources
0x101
Port2 TX Drop Packets
TX packets dropped due to lack of resources
0x103
Port1 RX Drop Packets
RX packets dropped due to lack of resources
0x104
Port2 RX Drop Packets
RX packets dropped due to lack of resources
Table 17. “All Ports Dropped Packet” MIB Counters Indirect Memory Offsets
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