參數(shù)資料
型號： KSZ8851-32MQLI
廠商： Micrel Inc
文件頁數(shù)： 55/88頁
文件大?。?/td> 0K
描述： IC CTLR MAC/PHY NON PCI 128PQFP
標(biāo)準(zhǔn)包裝： 66
控制器類型： 以太網(wǎng)控制器，MAC/PHY
接口： 總線
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
其它名稱： 576-3630
KSZ8851-32MQLI-ND
Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
August 2009
6
M9999-083109-2.0
Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1 ................................................................................ 56
Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2 ................................................................................ 56
Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3................................................................................ 56
0x5C – 0x5F: Reserved .................................................................................................................................................. 56
Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0 ........................................................................................ 56
Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1 ........................................................................................ 56
Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 ................................................................................ 56
Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 ................................................................................ 56
Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 ................................................................................ 57
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3................................................................................ 57
0x6C – 0x6F: Reserved .................................................................................................................................................. 57
Transmit Control Register (0x70 – 0x71): TXCR............................................................................................................ 57
Transmit Status Register (0x72 – 0x73): TXSR ............................................................................................................. 58
Receive Control Register 1 (0x74 – 0x75): RXCR1 ....................................................................................................... 58
Receive Control Register 2 (0x76 – 0x77): RXCR2 ....................................................................................................... 59
TXQ Memory Information Register (0x78 – 0x79): TXMIR ............................................................................................ 60
0x7A – 0x7B: Reserved .................................................................................................................................................. 60
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR ............................................................................... 60
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR...................................................................... 61
TXQ Command Register (0x80 – 0x81): TXQCR .......................................................................................................... 61
RXQ Command Register (0x82 – 0x83): RXQCR.......................................................................................................... 61
TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR............................................................................................. 62
RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR............................................................................................ 63
0x88 – 0x8B: Reserved .................................................................................................................................................. 63
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR ................................................................................. 63
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR ............................................................................ 64
Interrupt Enable Register (0x90 – 0x91): IER ................................................................................................................ 64
Interrupt Status Register (0x92 – 0x93): ISR ................................................................................................................. 65
0x94 – 0x9B: Reserved .................................................................................................................................................. 66
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR................................................................................. 66
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR ................................................................................... 66
MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0.................................................................................... 66
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1.................................................................................... 66
MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2.................................................................................... 67
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3.................................................................................... 67
0xA8 – 0xAF: Reserved.................................................................................................................................................. 67
Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR .................................................................................... 67
Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR................................................................................... 67
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR............................................................................. 67
0xB6 – 0xBF: Reserved.................................................................................................................................................. 68
Chip ID and Enable Register (0xC0 – 0xC1): CIDER .................................................................................................... 68
0xC2 – 0xC5: Reserved ................................................................................................................................................. 68
Chip Global Control Register (0xC6 – 0xC7): CGCR..................................................................................................... 68
Indirect Access Control Register (0xC8 – 0xC9): IACR ................................................................................................. 68
0xCA – 0xCF: Reserved ................................................................................................................................................. 69
Indirect Access Data Low Register (0xD0 – 0xD1): IADLR............................................................................................ 69
Indirect Access Data High Register (0xD2 – 0xD3): IADHR .......................................................................................... 69
Power Management Event Control Register (0xD4 – 0xD5): PMECR........................................................................... 69
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