參數(shù)資料
型號: KSZ8851-32MQLI
廠商: Micrel Inc
文件頁數(shù): 77/88頁
文件大?。?/td> 0K
描述: IC CTLR MAC/PHY NON PCI 128PQFP
標(biāo)準(zhǔn)包裝: 66
控制器類型: 以太網(wǎng)控制器,MAC/PHY
接口: 總線
電源電壓: 1.8V,2.5V,3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
其它名稱: 576-3630
KSZ8851-32MQLI-ND
Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
August 2009
8
M9999-083109-2.0
List of Figures
Figure 1. KSZ8851-16/32MQL/MQLI Functional Diagram ..................................................................................................... 1
Figure 2.128-Pin PQFP for 16-Bit ......................................................................................................................................... 10
Figure 3.128-Pin PQFP for 32-Bit ......................................................................................................................................... 16
Figure 4. Typical Straight Cable Connection ....................................................................................................................... 26
Figure 5. Typical Crossover Cable Connection ................................................................................................................... 27
Figure 6. Auto Negotiation and Parallel Operation .............................................................................................................. 28
Figure 7. KSZ8851M 8-Bit, 16-Bit, and 32-Bit Data Bus Connections ................................................................................ 33
Figure 8. Host TX Single Frame in Manual Enqueue Flow Diagram ................................................................................... 36
Figure 9. Host TX Multiple Frames in Auto- Enqueue Flow Diagram .................................................................................. 37
Figure 10. Host RX Single or Multiple Frames in Auto-Dequeue Flow Diagram ................................................................. 39
Figure 11. PHY Port 1 Near-end (Remote) and Host Far-end (Local) Loopback Paths ...................................................... 41
Figure 12. Asynchronous Cycle ........................................................................................................................................... 81
Figure 13. Address Latching Cycle for All Modes ................................................................................................................ 82
Figure 14. Auto Negotiation Timing ..................................................................................................................................... 83
Figure 15. Reset Timing ....................................................................................................................................................... 84
Figure 16. EEPROM Read Cycle Timing Diagram .............................................................................................................. 85
Figure 17. 128-Pin PQFP Package ...................................................................................................................................... 87
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