參數(shù)資料
型號: KSZ8873MLLJ
廠商: Micrel Inc
文件頁數(shù): 11/108頁
文件大小: 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
特色產(chǎn)品: KSZ8873MLLJ Ethernet Switches
標(biāo)準(zhǔn)包裝: 160
系列: *
其它名稱: 576-3996
PIC18F2420/2520/4420/4520
DS39631E-page 106
2008 Microchip Technology Inc.
TABLE 10-1:
PORTA I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
Type
Description
RA0/AN0
RA0
0
O
DIG
LATA<0> data output; not affected by analog input.
1
I
TTL
PORTA<0> data input; disabled when analog input enabled.
AN0
1
I
ANA
A/D input channel 0 and comparator C1- input. Default input
configuration on POR; does not affect digital output.
RA1/AN1
RA1
0
O
DIG
LATA<1> data output; not affected by analog input.
1
I
TTL
PORTA<1> data input; disabled when analog input enabled.
AN1
1
I
ANA
A/D input channel 1 and comparator C2- input. Default input
configuration on POR; does not affect digital output.
RA2/AN2/
VREF-/CVREF
RA2
0
O
DIG
LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.
1
I
TTL
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2
1
I
ANA
A/D input channel 2 and comparator C2+ input. Default input
configuration on POR; not affected by analog output.
VREF-
1
I
ANA
A/D and comparator voltage reference low input.
CVREF
x
O
ANA
Comparator voltage reference output. Enabling this feature disables
digital I/O.
RA3/AN3/VREF+RA3
0
O
DIG
LATA<3> data output; not affected by analog input.
1
I
TTL
PORTA<3> data input; disabled when analog input enabled.
AN3
1
I
ANA
A/D input channel 3 and comparator C1+ input. Default input
configuration on POR.
VREF+
1
I
ANA
A/D and comparator voltage reference high input.
RA4/T0CKI/C1OUT
RA4
0
O
DIG
LATA<4> data output.
1
I
ST
PORTA<4> data input; default configuration on POR.
T0CKI
1
I
ST
Timer0 clock input.
C1OUT
0
O
DIG
Comparator 1 output; takes priority over port data.
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
0
O
DIG
LATA<5> data output; not affected by analog input.
1
I
TTL
PORTA<5> data input; disabled when analog input enabled.
AN4
1
I
ANA
A/D input channel 4. Default configuration on POR.
SS
1
I
TTL
Slave select input for MSSP module.
HLVDIN
1
I
ANA
High/Low-Voltage Detect external trip point input.
C2OUT
0
O
DIG
Comparator 2 output; takes priority over port data.
OSC2/CLKO/RA6
RA6
0
O
DIG
LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
1
I
TTL
PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes
only.
OSC2
x
O
ANA
Main oscillator feedback output connection (XT, HS and LP modes).
CLKO
x
O
DIG
System cycle clock output (FOSC/4) in RC, INTIO1 and EC Oscillator
modes.
OSC1/CLKI/RA7
RA7
0
O
DIG
LATA<7> data output. Disabled in external oscillator modes.
1
I
TTL
PORTA<7> data input. Disabled in external oscillator modes.
OSC1
x
I
ANA
Main oscillator input connection.
CLKI
x
I
ANA
Main clock input connection.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x
= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
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