參數(shù)資料
型號: KSZ8873MLLJ
廠商: Micrel Inc
文件頁數(shù): 59/108頁
文件大?。?/td> 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
特色產(chǎn)品: KSZ8873MLLJ Ethernet Switches
標(biāo)準(zhǔn)包裝: 160
系列: *
其它名稱: 576-3996
Micrel, Inc.
KSZ8873MLLJ
September 2011
54
M9999-091911-1.8
Register 13 (0x0D): Global Control 11
Bit
Name
R/W
Description
Default
7-6
Tag_0x7
R/W
IEEE 802.1p mapping. The value in this field is used as the frame’s
priority when its IEEE 802.1p tag has a value of 0x7.
11
5-4
Tag_0x6
R/W
IEEE 802.1p mapping. The value in this field is used as the frame’s
priority when its IEEE 802.1p tag has a value of 0x6.
11
3-2
Tag_0x5
R/W
IEEE 802.1p mapping. The value in this field is used as the frame’s
priority when its IEEE 802.1p tag has a value of 0x5.
10
1-0
Tag_0x4
R/W
IEEE 802.1p mapping. The value in this field is used as the frame’s
priority when its IEEE 802.1p tag has a value of 0x4.
10
Register 14 (0x0E): Global Control 12
Bit
Name
R/W
Description
Default
7
Unknown
Packet
Default
Port
Enable
R/W
Send packets with unknown destination MAC addresses to specified
port(s) in bits [2:0] of this register.
=0, Disable
=1, Enable
0
6
Drive
Strength
of I/O Pad
R/W
=1, 16mA
=0, 8mA
1
5
Reserved
R/W
Reserved
Do not change the default values.
0
4
Reserved
RO
Reserved
0
3
Reserved
R/W
Reserved
Do not change the default values.
0
2-0
Unknown
Packet
Default
Port
R/W
Specify which port(s) to send packets with unknown destination MAC
addresses. This feature is enabled by bit [7] of this register.
Bit 2 stands for port 3.
Bit 1 stands for port 2.
Bit 0 stands for port 1.
An ‘1’ includes a port.
An ‘0’ excludes a port.
111
Register 15 (0x0F): Global Control 13
Bit
Name
R/W
Description
Default
7-3
PHY
Address
R/W
00000 : N/A
00001 : Port 1 PHY address is 0x1
00010 : Port 1 PHY address is 0x2
11101 : Port 1 PHY address is 0x29
11110 : N/A
11111 : N/A
Note:
Port 2 PHY address = (Port 1 PHY address) + 1
00001
2-0
Reserved
RO
Reserved
Do not change the default values.
000
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