參數(shù)資料
型號: KSZ8873MLLJ
廠商: Micrel Inc
文件頁數(shù): 78/108頁
文件大?。?/td> 0K
描述: IC ETHERNET SWITCH 3PORT 64LQFP
特色產(chǎn)品: KSZ8873MLLJ Ethernet Switches
標(biāo)準(zhǔn)包裝: 160
系列: *
其它名稱: 576-3996
Micrel, Inc.
KSZ8873MLLJ
September 2011
71
M9999-091911-1.8
Register 111 (0x6F): TOS Priority Control Register 15
Bit
Name
R/W
Description
Default
7-6
DSCP[127:126]
R/W
The value in this field is used as the frame’s priority when
bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value
is 0x3F.
00
5-4
DSCP[125:124]
R/W
The value in this field is used as the frame’s priority when
bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value
is 0x3E.
00
3-2
DSCP[123:122]
R/W
The value in this field is used as the frame’s priority when
bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value
is 0x3D.
00
1-0
DSCP[121:120]
R/W
The value in this field is used as the frame’s priority when
bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value
is 0x3C.
00
Registers 112 to 117
Registers 112 to 117 contain the switch engine’s MAC address. This 48-bit address is used as the Source Address for the
MAC’s full duplex flow control (PAUSE) frame.
Register 112 (0x70): MAC Address Register 0
Bit
Name
R/W
Description
Default
7-0
MACA[47:40]
R/W
0x00
Register 113 (0x71): MAC Address Register 1
Bit
Name
R/W
Description
Default
7-0
MACA[39:32]
R/W
0x10
Register 114 (0x72): MAC Address Register 2
Bit
Name
R/W
Description
Default
7-0
MACA[31:24]
R/W
0xA1
Register 115 (0x73): MAC Address Register 3
Bit
Name
R/W
Description
Default
7-0
MACA[23:16]
R/W
0xFF
Register 116 (0x74): MAC Address Register 4
Bit
Name
R/W
Description
Default
7-0
MACA[15:8]
R/W
0xFF
Register 117 (0x75): MAC Address Register 5
Bit
Name
R/W
Description
Default
7-0
MACA[7:0]
R/W
0xFF
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