hbwhelp@micrel.com or (408) 955-1690 2.3 Physical Tra" />
參數(shù)資料
型號(hào)： KSZ8993FL
廠商： Micrel Inc
文件頁(yè)數(shù)： 19/100頁(yè)
文件大小： 0K
描述： IC CONV MED 10/100 SGL 128PQFP
標(biāo)準(zhǔn)包裝： 66
系列： *
類型： *
應(yīng)用： *
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 1081 (CN2011-ZH PDF)
其它名稱： 576-1035
Micrel, Inc.
KS8993F/FL
June 2009
25
M9999-062509
hbwhelp@micrel.com or (408) 955-1690
2.3
Physical Transceiver
2.3.1
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to NRZI
conversion, MLT3 encoding and transmission. The circuit starts with a parallel to serial conversion, which converts the
MII data from the MAC into a 125 MHz serial bit stream. The data and control stream is then converted into 4B/5B
coding followed by a scrambler.
The serialized data is further converted from NRZ to NRZI format, and then
transmitted in MLT3 current output.
The output current is set by an external 1% 3.01 K
Ω resistor for the 1:1
transformer ratio.
It has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding
amplitude balance, overshoot and timing jitter.
The wave-shaped 10BASE-T output is also incorporated into the
100BASE-TX transmitter.
2.3.2
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3 to NRZI conversion, data
and clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding and serial to parallel conversion. The
receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust
its characteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation
based on comparisons of incoming signal strength against some known cable characteristics, then it tunes itself for
optimization. This is an ongoing process and can self adjust against environmental changes such as temperature
variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of base line wander and improve the dynamic range. The differential data conversion
circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler followed by the
4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
2.3.3
PLL Clock Synthesizer
The KS8993F generates 125 M
Ηz, 31.25 MHz, 25 MΗz and 10 MΗz clocks for system timing. Internal clocks are
generated from an external 25 MHz crystal or oscillator.
2.3.4
Scrambler/De-scrambler (100BASE-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline
wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The
scrambler can generate a 2047-bit non-repetitive sequence. The receiver will then de-scramble the incoming data
stream with the same sequence at the transmitter.
2.3.5
100BASE-FX Operation and Signal Detection
100BASE-FX operation is very similar to 100BASE-TX operation with the differences being that the scrambler/de-
scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In this mode, the auto negotiation
feature is bypassed since there is no standard that supports fiber auto negotiation, and the auto MDI/MDI-X feature is
also disabled.
相關(guān)PDF資料
PDF描述
KSZ8993MLI IC SWITCH 10/100 3PORT 128-PQFP
KSZ8993ML IC SWITCH 10/100 W/TXRX 128PQFP
KSZ8995FQ IC SWITCH 10/100 5PORT 128-PQFP
KSZ8995MA IC SWITCH 10/100 5PORT 128PQFP
KSZ8995MI IC SWITCH 5-PORT 10/100 128PQFP
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