參數(shù)資料
型號(hào): KSZ8993MI
廠商: Micrel Inc
文件頁(yè)數(shù): 24/86頁(yè)
文件大?。?/td> 0K
描述: IC SWITCH 10/100 W/TXRX 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 1081 (CN2011-ZH PDF)
其它名稱: 576-2124
KSZ8993MI-ND
Micrel, Inc.
KSZ8993M/ML
October 2008
30
M9999-020606
Switching Engine
The KSZ8993M features a high-performance switching engine to move data to and from the MACs’ packet
buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency.
The KSZ8993M has a 32kB internal frame buffer. This resource is shared between all three ports. The buffer-
sharing mode can be programmed through Global Register 2 (0x02). In one mode, ports are allowed to use any
free buffers in the buffer pool. In the second mode, each port is only allowed to use one third of the total buffer
pool. There are a total of 250 buffers available. Each buffer is sized at 128B.
MAC Operation
The KSZ8993M strictly abides by IEEE 802.3 standards to maximize compatibility.
Inter Packet Gap (IPG)
If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If
the current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN.
Back-Off Algorithm
The KSZ8993M implements the IEEE standard 802.3 binary exponential back-off algorithm, and optional
"aggressive mode" back-off. After 16 collisions, the packet will be optionally dropped depending on the chip
configuration in Global Register 3 (0x03)
Late Collision
If a transmit packet experiences collisions after 512 bit times of the transmission, the packet will be dropped.
Illegal Frames
The KSZ8993M discards frames less than 64 bytes and can be programmed to accept frames up to 1536 bytes in
Global Register 4 (0x04). For special applications, the KSZ8993M can also be programmed to accept frames up
to 1916 bytes in the same global register. Since the KSZ8993M supports VLAN tags, the maximum sizing is
adjusted when these tags are present. See the EEPROM section for programming options.
Flow Control
The KSZ8993M supports standard 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KSZ8993M receives a pause control frame, the KSZ8993M will not transmit the next
normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received
before the current timer expires, the timer will be updated with the new value in the second pause frame. During
this period (being flow controlled), only flow control packets from the KSZ8993M will be transmitted.
On the transmit side, the KSZ8993M has intelligent and efficient ways to determine when to invoke flow control.
The flow control is based on availability of the system resources, including available buffers, available transmit
queues and available receive queues.
The KSZ8993M will flow control a port, which just received a packet, if the destination port resource is being used
up. The KSZ8993M will issue a flow control frame (XOFF), containing the maximum pause time defined in IEEE
standard 802.3x. Once the resource is freed up, the KSZ8993M will send out the other flow control frame (XON)
with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided
to prevent the flow control mechanism from being activated and deactivated too many times.
The KSZ8993M will flow control all ports if the receive queue becomes full.
Half-Duplex Backpressure
A half-duplex backpressure option (Note: not in IEEE 802.3 standards) is also provided. The activation and
deactivation conditions are the same as the above in full duplex mode. If backpressure is required, the
KSZ8993M will send preambles to defer the other stations' transmission (carrier sense deference). To avoid
jabber and excessive deference defined in 802.3 standard, after a certain time it will discontinue the carrier sense
but it will raise the carrier sense quickly. This short silent time (no carrier sense) is to prevent other stations from
相關(guān)PDF資料
PDF描述
LFEC6E-3TN144C IC FPGA 6.1KLUTS 144TQFP
LFXP3E-5T144C IC FPGA 3.1KLUTS 100I/O 144-TQFP
LFXP3E-4T144I IC FPGA 3.1KLUTS 100I/O 144-TQFP
LFXP3C-5T144C IC FPGA 3.1KLUTS 100I/O 144-TQFP
LFXP3C-4T144I IC FPGA 3.1KLUTS 100I/O 144-TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KSZ8993ML 功能描述:以太網(wǎng) IC 2+1 Port 10/100 Switch w/Tranceivers & Frame Buffers, 128-Ld PQFP(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8993ML-EVAL 功能描述:以太網(wǎng)開(kāi)發(fā)工具 KSZ8993ML Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
KSZ8993MLI 功能描述:以太網(wǎng) IC 2+1 Port 10/100 Switch w/Tranceivers & Frame Buffers, 128-Ld PQFP(Lead Free, I-Temp) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8995FQ 功能描述:以太網(wǎng) IC Integrated 5-Port Switch with Fiber on Port 3 & 4, Lead free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8995FQ-EVAL 功能描述:以太網(wǎng)開(kāi)發(fā)工具 Integrated 5-Port Switch with Fiber on Port 3 & 4 Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓: