參數(shù)資料
型號: KSZ8993MI
廠商: Micrel Inc
文件頁數(shù): 57/86頁
文件大?。?/td> 0K
描述: IC SWITCH 10/100 W/TXRX 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-2124
KSZ8993MI-ND
Micrel, Inc.
KSZ8993M/ML
October 2008
60
M9999-020606
Register 27 (0x1B): Port 1 Control 11
Register 43 (0x2B): Port 2 Control 11
Register 59 (0x3B): Port 3 Control 11 (continued
Bit
Name
R/W
Description
Default
3
High priority
receive rate
flow control
enable
R/W
= 1, flow control may be asserted if the port’s
high priority receive rate is exceeded.
(To use this, differential receive rate control must
be on.)
= 0, flow control is not asserted if the port’s high
priority receive rate is exceeded.
0
2
Transmit
differential
priority rate
control
R/W
= 1, will do transmit rate control on both high and
low priority packets based on the rate counters
defined by the high and low priority packets
respectively.
= 0, will do transmit rate control on any packets.
The rate counters defined in low priority will be
used.
0
1
Low priority
transmit rate
control enable
R/W
1, enable the port’s low priority transmit rate
control feature
= 0, disable the port’s low priority transmit rate
control feature
0
High priority
transmit rate
control enable
R/W
= 1, enable the port’s high priority transmit rate
control feature
= 0, disable the port’s high priority transmit rate
control feature
0
Note: Port Control 12 and 13, and Port Status 0 contents can also be accessed with the MIIM (MDC/MDIO) interface via the
Standard MIIM registers.
Register 28 (0x1C): Port 1 Control 12
Register 44 (0x2C): Port 2 Control 12
Register 60 (0x3C): Reserved, not applied to port 3
Bit
Name
R/W
Description
Default
7
Auto
negotiation
enable
R/W
= 0, disable auto negotiation, speed and duplex
are decided by bit 6 and 5 of the same register.
= 1, auto negotiation is on
For port 1,
P1ANEN pin
value during
reset.
For port 2,
P2ANEN pin
value during
reset
6
Force speed
R/W
= 1, forced 100BT if AN is disabled (bit 7)
= 0, forced 10BT if AN is disabled (bit 7)
For port 1,
P1SPD pin
value during
reset.
For port 2,
P2SPD pin
value during
reset.
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