2C master mode by setting the KSZ8993M strap" />
參數(shù)資料
型號: KSZ8993MI
廠商: Micrel Inc
文件頁數(shù): 35/86頁
文件大?。?/td> 0K
描述: IC SWITCH 10/100 W/TXRX 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
其它名稱: 576-2124
KSZ8993MI-ND
Micrel, Inc.
KSZ8993M/ML
October 2008
40
M9999-020606
2.
Enable I
2C master mode by setting the KSZ8993M strap-in pins, PS[1:0] (pins 100 and 101, respectively) to
“00”.
3.
Check to ensure that the KSZ8993M reset signal input, RST_N (pin 67), is properly connected to the external
reset source at the board level.
4.
Program the desired configuration data into the EEPROM.
5.
Place the EEPROM on the board and power up the board.
6.
Assert an active-low reset to the RST_N pin of the KSZ8993M. After reset is de-asserted, the KSZ8993M will
begin reading the configuration data from the EEPROM. The KSZ8993M will check that the first byte read
from the EEPROM is “93”. If this value is correct, EEPROM configuration will continue. If not, EEPROM
configuration access is denied and all other data sent from the EEPROM will be ignored by the KSZ8993M.
The configuration access time (tprgm) is less than 15ms.
Note: For proper operation, check to ensure that the KSZ8993M PWRDN input signal (pin 36) is not asserted
during the reset operation. The PWRDN input is active low.
I
2C Slave Serial Bus Configuration
In managed mode, the KSZ8993M can be configured as an I
2C slave device. In this mode, an I2C master device
(external controller/CPU) has complete programming access to the KSZ8993M’s 128 registers. Programming
access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the
“Static MAC Table”, “VLAN Table”, “Dynamic MAC Table,” and “MIB Counters.” The tables and counters are
indirectly accessed via registers 110 thru 120.
In I
2C slave mode, the KSZ8993M operates like other I2C slave devices. Addressing the KSZ8993M’s 8 bit
registers is similar to addressing Atmel’s AT24C02 EEPROM’s memory locations. Details of I
2C read/write
operations and related timing information can be found in the AT24C02 Datasheet.
Two fixed 8 bits device addresses are used to address the KSZ8993M in I
2C slave mode. One is for read; the
other is for write. The addresses are as follow:
1011_1111 <read>
1011_1110 <write>
The following is a sample procedure for programming the KSZ8993M using the I
2C slave serial bus:
1.
Enable I
2C slave mode by setting the KSZ8993M strap-in pins PS[1:0] (pins 100 and 101, respectively) to
“01”.
2.
Power up the board and assert reset to the KSZ8993M. After reset, the “Start Switch” bit (register 1 bit 0) will
be set to ‘0’.
3.
Configure the desired register settings in the KSZ8993M, using the I
2C write operation.
4.
Read back and verify the register settings in the KSZ8993M, using the I
2C read operation.
5.
Write a ‘1’ to the “Start Switch” bit to start the KSZ8993M with the programmed settings.
Note: The “Start Switch” bit cannot be set to ‘0’ to stop the switch after an ‘1’ is written to this bit. Thus, it is
recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’.
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power
down” can be programmed after the switch has been started.
SPI Slave Serial Bus Configuration
In managed mode, the KSZ8993M can be configured as a SPI slave device. In this mode, a SPI master device
(external controller/CPU) has complete programming access to the KSZ8993M’s 128 registers. Programming
access includes the Global Registers, Port Registers, Advanced Control Registers and indirect access to the
“Static MAC Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters are
indirectly accessed via registers 110 thru 120.
The KSZ8993M supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data write.
SPI multiple read and multiple write are also supported by the KSZ8993M to expedite register read back and
register configuration, respectively.
相關(guān)PDF資料
PDF描述
LFEC6E-3TN144C IC FPGA 6.1KLUTS 144TQFP
LFXP3E-5T144C IC FPGA 3.1KLUTS 100I/O 144-TQFP
LFXP3E-4T144I IC FPGA 3.1KLUTS 100I/O 144-TQFP
LFXP3C-5T144C IC FPGA 3.1KLUTS 100I/O 144-TQFP
LFXP3C-4T144I IC FPGA 3.1KLUTS 100I/O 144-TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KSZ8993ML 功能描述:以太網(wǎng) IC 2+1 Port 10/100 Switch w/Tranceivers & Frame Buffers, 128-Ld PQFP(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8993ML-EVAL 功能描述:以太網(wǎng)開發(fā)工具 KSZ8993ML Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
KSZ8993MLI 功能描述:以太網(wǎng) IC 2+1 Port 10/100 Switch w/Tranceivers & Frame Buffers, 128-Ld PQFP(Lead Free, I-Temp) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8995FQ 功能描述:以太網(wǎng) IC Integrated 5-Port Switch with Fiber on Port 3 & 4, Lead free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8995FQ-EVAL 功能描述:以太網(wǎng)開發(fā)工具 Integrated 5-Port Switch with Fiber on Port 3 & 4 Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: