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參數(shù)資料
| 型號： | L033MU01RI |
| 廠商： | Spansion Inc. |
| 英文描述： | 32 Megabit (4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| 中文描述： | 32兆位（4個M × 8位）的MirrorBit⑩3.0伏特，只有統(tǒng)一部門閃存記憶體與VersatileI /輸出⑩控制 |
| 文件頁數(shù)： | 14/61頁 |
| 文件大?。?/td> | 772K |
| 代理商： | L033MU01RI |
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12
Am29LV033MU
September 12, 2006
D A T A S H E E T
Refer to the
DC Characteristics
table for the automatic
sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current. If RESET# is held at V
IL
but not within V
SS
±0.3 V, the standby current will be
greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The sys-
tem can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
READY
(not during Embedded Algo-
rithms). The system can read data t
RH
after the RE-
SET# pin returns to V
IH
.
Refer to the
AC Characteristics
tables for RESET# pa-
rameters and to Figure 16 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high
impedance state.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L033MU01VI | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| L033MU11RI | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| L033MU11VI | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| L033MU12RI | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
| L033MU12VI | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:32 Megabit (4 M x 8-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control |
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