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參數(shù)資料
| 型號： | L6260 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 運動控制電子 |
| 英文描述： | DISK DRIVE MOTOR CONTROLLER, 1.5 A, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大?。?/td> | 440K |
| 代理商： | L6260 |
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limit DAC.
The power circuits will be as shown in the follow-
ing figure 11.
Synth Hall
The Synth Hall pin can be programmed to provide
one of two possible output wave forms (see regis-
ter definitions). By setting the SYNTH_HALL bit in
register System Control Register B (4.5) to zero,
the signal is a once per BEMF crossing signal
which has the same phase as the BEMF amplifier
on chip with all the noise and false transitions re-
moved. With this bit set to one, a once per electri-
cal cycle signal with 50% duty cycle is produced.
Brake
The BRAKE mode commands a retract & then
turns on the lower three drivers, S_A_L, S_B_L
and S_C_L, to cause immediate braking of the
spindle.
Retract
The retract voltage is defined by a resistor to
ground from the RETRACT_V pin.
Test Circuits
1) I/O Mapping Test Mode. This mode is acti-
vated by taking the TEST pin high and hold-
ing the TRISTATE pin low. This puts the de-
vice into a test mode that allows certain pins
to be directly internally connected to other
pins for the purpose of testing continuity of
solder joints on a board. The following table
defines which pins are I/O mapped and which
is an input and which is an output. Notice that
I/O mapped pins in one group are not physi-
cally adjacent in the package allowing more
thorough testability.
INPUT PIN #
INPUT PIN
NAME
OUTPUT
PIN #
OUTPUT PIN
NAME
20
R/W11
SDIO
9
SLOAD
11
SDIO
10
SCLK
22
SYNTH_HALL
12
FCLK
22
SYNTH_HALL
50
UV1
5
POR
51
UV2
5
POR
2) Digital and Analog Test Mode. This mode is
activated by taking both the TEST pin and
TRISTATE pin high. Once this has been done
the SCLK pin of the serial interface is used to
clock out digital data through the DTEST pin.
Simultanously, the ATEST pin cycles through
carrying different analog signals from around
the chip.
SCLK
ATEST pin carries...
DTEST pin carries...
1
Nominal Bandgap Voltgage (normally 1.25V)
Postive/Negative incrementing of the FLL
2
Low Bandgap Voltage (normally 1.23V)
Spindle mask
3
Bias Voltage (normally 0.5V)
Spindle delay
4
Spindle DAC Output
FCLK/16 or FCLK/32 depending on
CLK_PRESCALE bit in System Control Reg B (4.4)
5
VCM DAC Output
BEMF Comparitor output (raw)
6
Temperature Shutdown Voltage (input - used to
alter the point at which thermal shutdown starts
operation)
VCM predriver (A)
7
Connected to the A gate of the spindles Low Side
Driver. Allows Rds(on) testing.
VCM predriver (F).
Sleep & Idle Functions
MODE
STATE
POWER LEVEL
POWER DISS.
Ready
Spin & VCM enabled
Full
20mA
Idle
Spin enabled, VCM disabled
Reduced
10mA
Sleep
Both spin and VCM disabled
Minimum
2mA (typical) 5mA (max)
INVALID
Spin disabled, VCM enabled*
Spindle set to low gain
If the spindle is disabled while the VCM is enabled the automatic parking function is invoked.
3) Tristate Test Mode. This mode is activated by
keeping the TEST pin low and taking the
TRISTATE pin high. This disables the digital
outputs, specifically SYNTH_HALL, POR &
SDIO.
4) No Test Modes. All test modes are disabled by
keeping the TEST pin & TRISTATE pin low
L6260
24/30
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