參數(shù)資料
型號(hào)： LA4064ZC-75TN48E
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 11/42頁(yè)
文件大?。?/td> 0K
描述： IC CPLD 64MACROCELLS 48TQFP
標(biāo)準(zhǔn)包裝： 250
系列： LA-ispMACH
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 1.7 V ~ 1.9 V
宏單元數(shù)： 64
輸入/輸出數(shù)： 32
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
19
LA-ispMACH 4000V/Z External Switching Characteristics
Over Recommended Operating Conditions
Parameter
Description
1, 2, 3
LA-ispMACH 4000V
-75
LA-ispMACH 4000Z
-75
Units
Min.
Max.
Min.
Max.
tPD
5-PT bypass combinatorial propagation delay
—
7.5
—
7.5
ns
tPD_MC
20-PT combinatorial propagation delay through macro-
cell
—
8.0
—
8.0
ns
tS
GLB register setup time before clock
4.5
—
4.5
—
ns
tST
GLB register setup time before clock with T-type regis-
ter
4.7
—
4.7
—
ns
tSIR
GLB register setup time before clock, input register
path
1.7
—
1.4
—
ns
tSIRZ
GLB register setup time before clock with zero hold
2.7
—
2.7
—
ns
tH
GLB register hold time after clock
0.0
—
0.0
—
ns
tHT
GLB register hold time after clock with T-type register
0.0
—
0.0
—
ns
tHIR
GLB register hold time after clock, input register path
1.0
—
1.3
—
ns
tHIRZ
GLB register hold time after clock, input register path
with zero hold
0.0
—
0.0
—
ns
tCO
GLB register clock-to-output delay
—
4.5
—
4.5
ns
tR
External reset pin to output delay
—
9.0
—
9.0
ns
tRW
External reset pulse duration
4.0
—
4.0
—
ns
tPTOE/DIS
Input to output local product term output enable/dis-
able
—
9.0
—
9.0
ns
tGPTOE/DIS
Input to output global product term output enable/dis-
able
—
10.3
—
10.5
ns
tGOE/DIS
Global OE input to output enable/disable
—
7.0
—
7.0
ns
tCW
Global clock width, high or low
2.8
—
2.8
—
ns
tGW
Global gate width low (for low transparent) or high (for
high transparent)
2.8
—
2.8
—
ns
tWIR
Input register clock width, high or low
2.8
—
2.8
—
ns
fMAX
4
Clock frequency with internal feedback
—
168
—
168
MHz
fMAX (Ext.) Clock frequency with external feedback, [1/ (tS + tCO)]
—
111
—
111
MHz
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
Timing v.3.2
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LA4064ZV-75TN100E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
LA4064ZV-75TN128E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
LA4064ZV-75TN144E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
LA4064ZV-75TN44E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
LA4064ZV-75TN48E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
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