參數(shù)資料
型號(hào)： LA4064ZC-75TN48E
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 20/42頁(yè)
文件大?。?/td> 0K
描述： IC CPLD 64MACROCELLS 48TQFP
標(biāo)準(zhǔn)包裝： 250
系列： LA-ispMACH
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 1.7 V ~ 1.9 V
宏單元數(shù)： 64
輸入/輸出數(shù)： 32
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 托盤
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
27
Signal Descriptions
LA-ispMACH 4000V ORP Reference Table
LA-ispMACH 4000Z ORP Reference Table
Signal Names
Description
TMS
Input – This pin is the IEEE 1149.1 Test Mode Select input, which is used to control
the state machine
TCK
Input – This pin is the IEEE 1149.1 Test Clock input pin, used to clock through the
state machine
TDI
Input – This pin is the IEEE 1149.1 Test Data In pin, used to load data
TDO
Output – This pin is the IEEE 1149.1 Test Data Out pin used to shift data out
GOE0/IO, GOE1/IO
These pins are congured to be either Global Output Enable Input or as general I/O
pins
GND
Ground
NC
Not Connected
VCC
The power supply pins for the logic core and JTAG port
CLK0/I, CLK1/I, CLK2/I, CLK3/I
These pins are congured to be either CLK input or as an input
VCCO0, VCCO1
The power supply pins for each I/O bank
yzz
Input/Output
1 – These are the general purpose I/O used by the logic array. y is GLB
reference (alpha) and z is macrocell reference (numeric). z: 0-15
LA-ispMACH 4032V/Z
y: A-B
LA-ispMACH 4064V/Z
y: A-D
LA-ispMACH 4128V/Z
y: A-H
1. In some packages, certain I/Os are only available for use as inputs. See the signal connections table for details.
4032V
4064V
4128V
Number of I/Os
30
1
32
30
2
32
64
92
3
96
Number of GLBs
2244
4
8
88
Number of I/Os /GLB
16
8
16
8
12
Reference ORP Table
16 I/Os / GLB
8 I/Os / GLB
16 I/Os / GLB 8 I/Os /GLB
12 I/Os / GLB
1. 32-macrocell device, 44 TQFP: 2 GLBs have 15 out of 16 I/Os bonded out.
2. 64-macrocells device, 44 TQFP: 2 GLBs have 7 out of 8 I/Os bonded out.
3. 128-macrocell device, 128 TQFP: 4 GLBs have 11 out of 12 I/Os
4032Z
4064Z
4128Z
Number of I/Os
32
64
Number of GLBs
2448
Number of I/Os / GLB
16
8
16
8
Reference ORP Table
16 I/Os /
GLB
8 I/Os /
GLB
16 I/Os /
GLB
8 I/Os /
GLB
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LA4064ZV-75TN100E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
LA4064ZV-75TN128E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
LA4064ZV-75TN144E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
LA4064ZV-75TN44E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
LA4064ZV-75TN48E 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/1.8V In-System Programmable SuperFAST High Density PLDs
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