參數(shù)資料
型號(hào): LAMXO640E-3TN100E
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 2/77頁(yè)
文件大小: 0K
描述: IC FPGA 640LUTS 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: LA-MachXO
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 4.9ns
電壓電源 - 內(nèi)部: 1.14 V ~ 1.26 V
宏單元數(shù): 320
輸入/輸出數(shù): 74
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤(pán)
2-7
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock/Control Distribution Network
The LA-MachXO automotive family of devices provides global signals that are available to all PFUs. These signals
consist of four primary clocks and four secondary clocks. Primary clock signals are generated from four 16:1 muxes
as shown in Figure 2-7 and Figure 2-8. The available clock sources for the LA-MachXO256 and LA-MachXO640
devices are four dual function clock pins and 12 internal routing signals. The available clock sources for the LA-
MachXO1200 and LA-MachXO2280 devices are four dual function clock pins, up to nine internal routing signals
and up to six PLL outputs.
Figure 2-7. Primary Clocks for LA-MachXO256 and LA-MachXO640 Devices
Routing
Clock
Pads
Primary Clock 0
Primary Clock 1
Primary Clock 2
Primary Clock 3
4
12
16:1
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LAMXO640E-3TN144E 功能描述:CPLD - 復(fù)雜可編程邏輯器件 Auto Grade (AEC-Q100 ) MachXO640E RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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