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參數(shù)資料
| 型號(hào)： | LAN8700 |
| 廠商： | SMSC Corporation |
| 英文描述： | 【15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint |
| 中文描述： | 【15kV的ESD保護(hù)信息產(chǎn)業(yè)部/ RMII快速的HP Auto - MDIX功能和SMSC flexPWR商標(biāo)以太網(wǎng)PHY在小尺寸 |
| 文件頁(yè)數(shù)： | 12/73頁(yè) |
| 文件大小： | 457K |
| 代理商： | LAN8700 |
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±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR
TM
in a Small Footprint
Datasheet
Revision 1.0 (02-09-07)
12
SMSC LAN8700/LAN8700I
DATASHEET
Chapter 3 Pin Description
This chapter describes the signals on each pin. When a lower case “n” is used at the beginning of the
signal name, it indicates that the signal is active low. For example, nRST indicates that the reset signal
is active low.
3.1
I/O Signals
I
Input. Digital LVCMOS levels.
O
Output. Digital LVCMOS levels.
I/O
Input or Output. Digital LVCMOS levels.
Note:
The digital signals are not 5V tolerant.They are variable voltage from +1.6V to +3.6V.
AI
Input. Analog levels.
AO
Output. Analog levels.
Table 3.1 MII Signals
SIGNAL NAME
TYPE
DESCRIPTION
TXD0
I
Transmit Data 0
: Bit 0 of the 4 data bits that are accepted by
the PHY for transmission.
TXD1
I
Transmit Data 1
: Bit 1 of the 4 data bits that are accepted by
the PHY for transmission.
TXD2
I
Transmit Data 2
: Bit 2 of the 4 data bits that are accepted by
the PHY for transmission
Note:
This signal should be grounded in RMII Mode.
TXD3
I
Transmit Data 3
:
Bit 3 of the 4 data bits that are accepted by
the PHY for transmission.
Note:
This signal should be grounded in RMII Mode
nINT/
TX_ER/
TXD4
I/O
MII Transmit Error
: When driven high, the 4B/5B encode
process substitutes the Transmit Error code-group (/H/) for the
encoded data word. This input is ignored in 10Base-T operation.
MII Transmit Data 4:
In Symbol Interface (5B Decoding) mode,
this signal becomes the MII Transmit Data 4 line, the MSB of the
5-bit symbol code-group.
Notes:
This signal is not used in RMII Mode.
This signal is mux’d with nINT
See
Section 4.10, "nINT/TX_ER/TXD4 Strapping," on page 30
for additional information on configuration/strapping options.
TX_EN
I
Transmit Enable
: Indicates that valid data is presented on the
TXD[3:0] signals, for transmission. In RMII Mode, only TXD[1:0]
have valid data.
TX_CLK
O
Transmit Clock
: 25MHz in 100Base-TX mode. 2.5MHz in
10Base-T mode.
Note:
This signal is not used in RMII Mode
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