
SMSC LAN9117
DATASHEET
Revision 1.1 (05-17-05)
Datasheet
PRODUCT FEATURES
LAN9117
High Performance
Single-Chip 10/100 Non-
PCI Ethernet Controller
Highlights
■
Member of LAN9118 Family;optimized for medium-
high performance applications
■
Easily interfaces to most 16-bit embedded CPU’s
■
Efficient architecture with low CPU overhead
■
Integrated PHY; supports external PHY via MII
interface
■
Supports audio & video streaming over Ethernet:
1-2 high-definition (HD) MPEG2 streams
■
Medium-high speed member of LAN9118 Family
(all members are pin-compatible)
Target Applications
■
Medium-range Cable, satellite, and IP set-top boxes
■
Digital video recorders and DVD recorders/players
■
High definition televisions
■
Digital media clients/servers and home gateways
■
Video-over IP Solutions, IP PBX & video phones
■
Wireless routers & access points
■
High-end audio distribution systems
Key Benefits
■
Non-PCI Ethernet Controler for medium-high
performance applications
—
16-bit interface with fast bus cycle times
—
Burst-mode read support
—
External MII Interface
■
Eliminates dropped packets
—
Internal buffer memory can store over 200 packets
—
Supports automatic or host-triggered PAUSE and back-
pressure flow control
■
Minimizes CPU overhead
—
Supports Slave-DMA
—
Interrupt Pin with Programmable Hold-off timer
■
Reduces system cost and increases design flexibility
—
SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
—
Low-cost, low--pin count non-PCI interface for
embedded designs
■
Reduced Power Modes
—
Numerous power management modes
—
Wake on LAN*
—
Magic packet wakeup*
—
Wakeup indicator event signal
—
Link Status Change
■
Single chip Ethernet controller
—
Fully compliant with IEEE 802.3/802.3u standards
—
Integrated Ethernet MAC and PHY
—
10BASE-T and 100BASE-TX support
—
Full- and Half-duplex support
—
Full-duplex flow control
—
Backpressure for half-duplex flow control
—
Preamble generation and removal
—
Automatic 32-bit CRC generation and checking
—
Automatic payload padding and pad removal
—
Loop-back modes
■
Flexible address filtering modes
—
One 48-bit perfect address
—
64 hash-filtered multicast addresses
—
Pass all multicast
—
Promiscuous mode
—
Inverse filtering
—
Pass all incoming with status report
—
Disable reception of broadcast packets
■
Integrated Ethernet PHY
—
Auto-negotiation
—
Automatic polarity detection and correction
■
High-Performance host bus interface
—
Simple, SRAM-like interface
—
16-bit data bus
—
Large, 16Kbyte FIFO memory that can be allocated to
RX or TX functions
—
One configurable host interrupt
■
Miscellaneous features
—
Low profile 100-pin TQFP package; green, lead free
package also availaible
—
Integral 1.8V regulator
—
General Purpose Timer
—
Support for optional EEPROM
—
Support for 3 status LEDs multiplexed with
Programmable GPIO signals
■
3.3V Power Supply with 5V tolerant I/O
■
0 to 70
°
C
*
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