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參數(shù)資料
| 型號： | LAN8700 |
| 廠商： | SMSC Corporation |
| 英文描述： | 【15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint |
| 中文描述： | 【15kV的ESD保護信息產(chǎn)業(yè)部/ RMII快速的HP Auto - MDIX功能和SMSC flexPWR商標以太網(wǎng)PHY在小尺寸 |
| 文件頁數(shù)： | 48/73頁 |
| 文件大?。?/td> | 457K |
| 代理商： | LAN8700 |
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±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR
TM
in a Small Footprint
Datasheet
Revision 1.0 (02-09-07)
48
SMSC LAN8700/LAN8700I
DATASHEET
5.3.1
Primary Interrupt System
The Primary Interrupt system is the default interrupt mode, (Bit 17.6 = ‘0’). The Primary Interrupt
System is always selected after power-up or hard reset.
To set an interrupt, set the corresponding mask bit in the interrupt Mask register 30 (see
Table 5.45
).
Then when the event to assert nINT is true, the nINT output will be asserted.
When the corresponding Event to De-Assert nINT is true, then the nINT will be de-asserted.
Note:
The ENERGYON bit 17.1 is defaulted to a ‘1’ at the start of the signal acquisition process,
therefore the Interrupt source flag 29.7 will also read as a ‘1’ at power-up. If no signal is
present, then both 17.1 and 29.7 wil clear within a few milliseconds.
5.3.2
Alternate Interrupt System
The Alternative method is enabled by writing a ‘1’ to 17.6 (ALTINT).
To set an interrupt, set the corresponding bit of the in the Mask Register 30, (see
Table 5.46
).
To Clear an interrupt, either clear the corresponding bit in the Mask Register (30), this will de-assert
the nINT output, or Clear the Interrupt Source, and write a ‘1’ to the corresponding Interrupt Source
Flag. Writing a ‘1’ to the Interrupt Source Flag will cause the state machine to check the Interrupt
Source to determine if the Interrupt Source Flag should clear or stay as a ‘1’. If the Condition to De-
Assert is true, then the Interrupt Source Flag is cleared, and the nINT is also de-asserted. If the
Condition to De-Assert is false, then the Interrupt Source Flag remains set, and the nINT remains
asserted.
For example 30.7 is set to ‘1’ to enable the ENERGYON interrupt. After a cable is plugged in,
ENERGYON (17.1) goes active and nINT will be asserted low.
Table 5.45 Interrupt Management Table.
Mask
Interrupt Source Flag
Interrupt Source
Event to Assert nINT
Event to De-Assert nINT
30.7
29.7
ENERGYON
17.1
ENERGYON
Rising 17.1
a
a.
If the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high, nINT will assert for
256 ms, approximately one second after ENERGYON goes low when the Cable is unplugged. To prevent an
unexpected assertion of nINT, the ENERGYON interrupt mask should always be cleared as part of the
ENERGYON interrupt service routine.
Falling 17.1 or
Reading register 29
30.6
29.6
Auto-Negotiation
complete
1.5
Auto-Negotiate
Complete
Rising 1.5
Falling 1.5 or
Reading register 29
30.5
29.5
Remote Fault Detected
1.4
Remote Fault
Rising 1.4
Falling 1.4, or
Reading register 1 or
Reading register 29
30.4
29.4
Link Down
1.2
Link Status
Falling 1.2
Reading register 1 or
Reading register 29
30.3
29.3
Auto-Negotiation LP
Achnowledge
5.14
Acknowledge
Rising 5.14
Falling 5.14 or
Read register 29
30.2
29.2
Parallel Detection Fault
6.4
Parallel Detection
Fault
Rising 6.4
Falling 6.4 or
Reading register 6, or
Reading register 29 or
Re-AutoNegotaite or
Link down
30.1
29.1
Auto-Negotiation Page
Received
6.1
Page Received
Rising 6.1
Falling of 6.1 or
Reading register 6, or
Reading register 29
Re-AutoNegotatie, or
Link Down.
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