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參數(shù)資料
| 型號： | LAN8700 |
| 廠商： | SMSC Corporation |
| 英文描述： | 【15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint |
| 中文描述： | 【15kV的ESD保護(hù)信息產(chǎn)業(yè)部/ RMII快速的HP Auto - MDIX功能和SMSC flexPWR商標(biāo)以太網(wǎng)PHY在小尺寸 |
| 文件頁數(shù)： | 51/73頁 |
| 文件大小： | 457K |
| 代理商： | LAN8700 |
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±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR
TM
in a Small Footprint
Datasheet
SMSC LAN8700/LAN8700I
51
Revision 1.0 (02-09-07)
DATASHEET
The Phy has an internal Power-On-Reset (POR) signal which is asserted for 21ms following a VDD33
(+3.3V) and VDDCORE (+1.8V) power-up. This internal POR is internally “OR”-ed with the nRST input.
During a Hardware reset, either external or POR, an external clock
must
be supplied to the CLKIN
signal.
Software (SW) reset
: Activated by writing register 0, bit 15 high. This signal is self- clearing. After the
register-write, internal logic extends the reset by 256μs to allow PLL-stabilization before releasing the
logic from reset.
The IEEE 802.3u standard, clause 22 (22.2.4.1.1) states that the reset process should be completed
within 0.5s from the setting of this bit.
Power-Down reset
: Automatically activated when the PHY comes out of power-down mode. The
internal power-down reset is extended by 256μs after exiting the power-down mode to allow the PLLs
to stabilize before the logic is released from reset.
These 3 reset sources are combined together in the digital block to create the internal “general reset”,
SYSRST, which is an asynchronous reset and is active HIGH. This SYSRST directly drives the PCS,
DSP and MII blocks. It is also input to the Central Bias block in order to generate a short reset for the
PLLs.
The SMI mechanism and registers are reset only by the Hardware and Software resets. During Power-
Down, the SMI registers are not reset. Note that some SMI register bits are not cleared by Software
reset – these are marked “NASR” in the register tables.
For the first 16us after coming out of reset, the MII will run at 2.5 MHz. After that it will switch to 25
MHz if auto-negotiation is enabled.
5.4.7
LED Description
The PHY provides four LED signals. These provide a convenient means to determine the mode of
operation of the Phy. All LED signals are either active high or active low.
The four LED signals can be either active-high or active-low. Polarity depends upon the Phy address
latched in on reset. The LAN8700/LAN8700I senses each Phy address bit and changes the polarity of
the LED signal accordingly. If the address bit is set as level “1”, the LED polarity will be set to an active-
low. If the address bit is set as level “0”, the LED polarity will be set to an active-high.
The ACTIVITY LED output is driven active when CRS is active (high). When CRS becomes inactive,
the Activity LED output is extended by 128ms.
The
LINK LED output is driven active whenever the PHY detects a valid link. The use of the 10Mbps
or 100Mbps link test status is determined by the condition of the internally determined speed selection.
The SPEED100 LED output is driven active when the operating speed is 100Mbit/s or during Auto-
negotiation. This LED will go inactive when the operating speed is 10Mbit/s or during line isolation
(register 31 bit 5).
The Full-Duplex LED output is driven active low when the link is operating in Full-Duplex mode.
5.4.8
Loopback Operation
The 10/100 digital has two independent loop-back modes: Internal loopback and far loopback.
5.4.8.1
Internal Loopback
The internal loopback mode is enabled by setting bit register 0 bit 14 to logic one. In this mode, the
scrambled transmit data (output of the scrambler) is looped into the receive logic (input of the
descrambler). The COL signal will be inactive in this mode, unless collision test (bit 0.7) is active.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| LAN8700AEZG | 制造商:SMSC 功能描述: |
| LAN8700-AEZG | 功能描述:以太網(wǎng) IC HIPERFRM ETHRNT PHY RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN8700C-AEZG | 功能描述:以太網(wǎng) IC IC w/HP Auto-MDIX Embedded Ethernet RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN8700C-AEZG-AR2 | 制造商:Microchip Technology Inc 功能描述: 制造商:Microchip Technology Inc 功能描述:MII/RMII 10/100 ETHERNET TRANSCEIVER - Trays 制造商:Microchip Technology Inc 功能描述:TXRX ETHERNET 10/100 36-VQFN 制造商:Microchip Technology Inc 功能描述:Ethernet ICs MII/RMII 10/100 制造商:Microchip Technology Inc 功能描述:MII/RMII 10/100 Ethernet Transceiver, 36 VQFN 6x6x0.9 TRAY |
| LAN8700C-AEZG-TR | 功能描述:以太網(wǎng) IC Hi Perform Ethernet PHY RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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