參數(shù)資料
型號： LAN91C100FDTQFP
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
中文描述： 2 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208
封裝： TQFP-208
文件頁數(shù)： 31/79頁
文件大小： 585K
代理商： LAN91C100FDTQFP
FEAST Fast Ethernet Controller with Full Duplex Capability
SMSC DS – LAN91C100FD Rev. D
Page 31
Rev.
10/14/2002
PRELIMINARY
The three command bits determine the command issued as described below:
HIGH
BYTE
LOW
BYTE
COMMAND
0
0
N2
N1
N0/BUSY
x
y
z
0
COMMAND SET:
xyz
000
0)
NOOP - NO OPERATION
001
1)
ALLOCATE MEMORY FOR TX - N2,N1,N0 defines the amount of memory requested as
(value + 1) * 256 bytes. Namely N2,N1,N0 = 1 will request 2 * 256 = 512 bytes. A shift-based
divide by 256 of the packet length yields the appropriate value to be used as N2,N1,N0.
Immediately generates a completion code at the ALLOCATION RESULT REGISTER. Can
optionally generate an interrupt on successful completion. N2,N1,N0 are ignored by the
LAN91C100FD but should be implemented in LAN91C100FD software drivers for LAN9000
compatibility.
010
2)
RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant interrupts,
resets packet FIFO pointers.
011
3)
REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU has completed
processing of present receive frame. This command removes the receive packet number from
the RX FIFO and brings the next receive frame (if any) to the RX area (output of RX FIFO).
100
4)
REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases all memory used by
the packet presently at the RX FIFO output. The MMU busy time after issuing REMOVE and
RELEASE command depends on the time when the busy bit is cleared. The time from issuing
REMOVE and RELEASE command on the last receive packet to the time when receive FIFO
is empty depends on RX INT bit turning low. An alternate approach can be checking the read
RX FIFO register.
101
5)
RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified in the
PACKET NUMBER REGISTER. Should not be used for frames pending transmission.
Typically used to remove transmitted frames, after reading their completion status. Can be
used following 3) to release receive packet memory in a more flexible way than 4).
110
6)
ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a
packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET
NUMBER REGISTER.
111
7)
RESET TX FIFOs - This command will reset both TX FIFOs: The TX FIFO holding the packet
numbers awaiting transmission and the TX Completion FIFO. This command provides a
mechanism for canceling packet transmissions, and reordering or bypassing the transmit
queue. The RESET TX FIFOs command should only be used when the transmitter is
disabled. Unlike the RESET MMU command, the RESET TX FIFOs does not release any
memory.
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
LAN91C100QFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述:
LAN91C100QFP WAF 制造商:SMSC 功能描述:
LAN91C110 制造商:SMSC 制造商全稱:SMSC 功能描述:FEAST FAST ETHERNET CONTROLLER FOR PCMCIA AND GENERIC 16-BIT APPLICATIONS
LAN91C110-JD 制造商:SMSC 功能描述:
LAN91C110-PU 功能描述:以太網(wǎng) IC Non-PCI 10/100 Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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