- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358741 > LAN91C100FDTQFP (STANDARD MICROSYSTEMS CORP) FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY PDF資料下載
參數(shù)資料
| 型號(hào)： | LAN91C100FDTQFP |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY |
| 中文描述： | 2 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封裝： | TQFP-208 |
| 文件頁數(shù)： | 41/79頁 |
| 文件大?。?/td> | 585K |
| 代理商： | LAN91C100FDTQFP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當(dāng)前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁
FEAST Fast Ethernet Controller with Full Duplex Capability
SMSC DS – LAN91C100FD Rev. D
Page 41
Rev.
10/14/2002
PRELIMINARY
5.2
Typical Flow of Events for Transmit (Auto Release = 0)
S/W DRIVER
MAC SIDE
1 ISSUE ALLOCATE MEMORY FOR TX - N
BYTES - the MMU attempts to allocate N bytes
of RAM.
2 WAIT FOR SUCCESSFUL COMPLETION
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
3 LOAD TRANSMIT DATA - Copy the TX packet
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed until a
transmit interrupt is generated.
5
The enqueued packet will be transferred to the
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duplex mode
only) state.
a) Upon transmit completion the first word in
memory is written with the status word. The
packet number is moved from the TX FIFO
into the TX completion FIFO. Interrupt is
generated by the TX completion FIFO being
not empty.
b) If a TX failure occurs on any packets, TX
INT is generated and TXENA is cleared,
transmission sequence stops. The packet
number of the failure packet is presented at
the TX FIFO PORTS Register.
6
7 a) SERVICE INTERRUPT - Read Interrupt
Status Register. If it is a transmit interrupt,
read the TX FIFO Packet Number from the
FIFO Ports Register. Write the packet
number into the Packet Number Register.
The corresponding status word is now
readable from memory. If status word
shows successful transmission, issue
RELEASE packet number command to free
up the memory used by this packet.
Remove packet number from completion
FIFO by writing TX INT Acknowledge
Register.
b) Option 1) Release the packet.
Option 2) Check the transmit status in the
EPH STATUS Register, write the packet
number of the current packet to the Packet
Number Register, re-enable TXENA, then
go to step 4 to start the TX sequence again.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LAN91C100 | FEAST⑩ Fast Ethernet Controller |
| LAN91C110 | FEAST FAST ETHERNET CONTROLLER FOR PCMCIA AND GENERIC 16-BIT APPLICATIONS |
| LAN91C96(100TQFP) | LAN Node Controller |
| LAN91C96(100QFP) | LAN Node Controller |
| LAN91C95 | LAN Node Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LAN91C100QFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述: |
| LAN91C100QFP WAF | 制造商:SMSC 功能描述: |
| LAN91C110 | 制造商:SMSC 制造商全稱:SMSC 功能描述:FEAST FAST ETHERNET CONTROLLER FOR PCMCIA AND GENERIC 16-BIT APPLICATIONS |
| LAN91C110-JD | 制造商:SMSC 功能描述: |
| LAN91C110-PU | 功能描述:以太網(wǎng) IC Non-PCI 10/100 Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。