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參數(shù)資料
| 型號： | LC5512MC-45F256C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| 中文描述： | EE PLD, 5.7 ns, PBGA256 |
| 封裝： | FPBGA-256 |
| 文件頁數(shù)： | 21/92頁 |
| 文件大?。?/td> | 378K |
| 代理商： | LC5512MC-45F256C |
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
21
sysCONFIG Interface
In addition to being able to program the device through the IEEE 1532 interface a microprocessor style interface
(sysCONFIG interface) allows recon
fi
guration of the SRAM bits within the device. For more information on the
sysCONFIG capability, please refer to technical note number TN1026,
ispXP Configuration Usage Guidelines.
Security Scheme
A programmable security scheme is provided on the ispXPLD 5000MX devices as a deterrent to unauthorized
copying of the array con
fi
guration patterns. Once programmed, this bit prevents readback of the programmed pat-
tern by a device programmer, securing proprietary designs from competitors. The security bit also prevents pro-
gramming and veri
fi
cation. The entire device must be erased in order to erase the security bit.
Low Power Consumption
The ispXPLD 5000MX devices use zero power non-volatile cells along with full CMOS design to provide low static
power consumption. The 1.8V core reduces dynamic power consumption compared with devices with higher core
voltages. For information on estimating power consumption, please refer to Lattice technical note number TN1031,
Power Estimation in ispXPLD 5000MX Devices.
Density Migration
The ispXPLD 5000MX family has been designed to ensure that different density devices in the same package have
compatible pin-outs. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is possible to shift a lower utilization design tar-
geted for a high-density device to a lower density device. However, the exact details of the
fi
nal resource utilization
will impact the likely success in each case.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispXPLD 5000MX devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This
allows functional testing of the circuit board on which the device is mounted through a serial scan path that can
access all critical logic notes. Internal boundary scan registers are linked internally, allowing test data to be shifted
in and loaded directly onto test nodes, or test node data to be captured and shifted out for veri
fi
cation. In addition,
these devices can be linked into a board-level serial scan path for board-level testing. The test access port has its
own supply voltage and can operate with LVCMOS3.3, 2.5 and 1.8V standards.
sysIO Quick Con
fi
guration
To facilitate the most ef
fi
cient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for con
fi
guration of the I/Os’
physical nature should be minimal so that board test time is minimized. The ispXPLD 5000MX family of devices
allows this by offering the user the ability to quickly con
fi
gure the physical nature of the sysIO cells. This quick con-
fi
guration takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lat-
tice’s ispVM System programming software can either perform the quick con
fi
guration through the PC parallel
port, or can generate the ATE or test vectors necessary for a third-party test system.
相關(guān)PDF資料 |
PDF描述 |
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| LC5512MC-45F484C | 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-45Q208C | 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-75F256C | 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-75F484C | 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-75Q208C | 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC5512MC-45F256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-45F484C | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC5512MC-45F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-45F672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MC-45F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
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