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參數(shù)資料

型號：	LC5512MC-45F256C
廠商：	LATTICE SEMICONDUCTOR CORP
元件分類：	PLD
英文描述：	3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
中文描述：	EE PLD, 5.7 ns, PBGA256
封裝：	FPBGA-256
文件頁數(shù)：	37/92頁
文件大?。?/td>	378K
代理商：	LC5512MC-45F256C

Lattice Semiconductor

ispXPLD 5000MX Family Data Sheet

37

t

SPADDH

Address Hold time

after Clock Time

R/W Setup before

Clock Time

R/W Hold time after

Clock Time

Data Setup before

Clock Time

Data Hold time after

Clock Time

Clock to Output

Delay

Reset to RAM

Output Delay

Reset Recovery

Time

Reset Pulse Width

—

-0.01

—

-0.01

—

-0.01

—

-0.01

—

-0.01

—

ns

t

SPRWS

—

-0.27

—

-0.27

—

-0.27

—

-0.27

—

-0.21

—

ns

t

SPRWH

—

-0.01

—

-0.01

—

-0.01

—

-0.01

—

-0.01

—

ns

t

SPDATAS

—

-0.27

—

-0.27

—

-0.27

—

-0.27

—

-0.21

—

ns

t

SPDATAH

—

-0.01

—

-0.01

—

-0.01

—

-0.01

—

-0.01

—

ns

t

SPCLKO

—

—

5.97

—

5.97

—

5.97

—

5.97

—

9.86

ns

t

SPRSTO

—

—

3.30

—

3.30

—

3.30

—

3.30

—

4.29

ns

t

SPRSTR

—

1.20

—

1.20

—

1.20

—

1.20

—

1.56

—

ns

t

SPRSTPW

Pseudo Dual Port RAM

—

0.14

—

0.14

—

0.14

—

0.14

—

0.19

—

ns

t

PDPMSS

Memory Select

Setup Before Clock

Memory Select

Hold time after

Clock

Clock Enable Setup

before Read Clock

Time

Clock Enable Hold

time after Read

Clock Time

Clock Enable Setup

before Write Clock

Time

Clock Enable Hold

time after Write

Clock Time

Read Address

Setup before Read

Clock Time

Read Address Hold

after Read Clock

Time

Write Address

Setup before Write

Clock Time

Write Address Hold

after Write Clock

Time

R/W Setup before

Clock Time

—

-0.27

—

-0.27

—

-0.22

—

-0.22

—

-0.21

—

ns

t

PDPMSH

—

-0.01

—

-0.01

—

-0.01

—

-0.01

—

-0.01

—

ns

t

PDPRCES

—

2.33

—

2.33

—

2.91

—

2.91

—

3.03

—

ns

t

PDPRCEH

—

-2.95

—

-2.95

—

-2.36

—

-2.36

—

-2.27

—

ns

t

PDPWCES

—

1.87

—

1.87

—

2.34

—

2.34

—

2.43

—

ns

t

PDPWCEH

—

-2.95

—

-2.95

—

-2.36

—

-2.36

—

-2.27

—

ns

t

PDPRADDS

—

-0.27

—

-0.27

—

-0.22

—

-0.22

—

-0.21

—

ns

t

PDPRADDH

—

-0.01

—

-0.01

—

-0.01

—

-0.01

—

-0.01

—

ns

t

PDPWADDS

—

-0.27

—

-0.27

—

-0.22

—

-0.22

—

-0.21

—

ns

t

PDPWADDH

—

-0.01

—

-0.01

—

-0.01

—

-0.01

—

-0.01

—

ns

t

PDPRWS

—

-0.27

—

-0.27

—

-0.22

—

-0.22

—

-0.21

—

ns

ispXPLD 5000MX Family Internal Switching Characteristics (Continued)

Over Recommended Operating Conditions

Parameter

Description

Base

Parameter

-4

-45

-5

-52

-75

Units

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

相關(guān)PDF資料	PDF描述
LC5512MC-45F484C	3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-45Q208C	3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-75F256C	3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-75F484C	3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-75Q208C	3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
LC5512MC-45F256I	制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-45F484C	功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5512MC-45F484I	制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-45F672C	制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-45F672I	制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family

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