參數(shù)資料
型號(hào): LC5512MC-45F256C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
中文描述: EE PLD, 5.7 ns, PBGA256
封裝: FPBGA-256
文件頁(yè)數(shù): 27/92頁(yè)
文件大?。?/td> 378K
代理商: LC5512MC-45F256C
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
27
sysIO Single Ended DC Electrical Characteristics
Over Recommended Operating Conditions
Input/Output
Standard
V
IL
V
IH
V
OL
Max (V)
V
OH
Min (V)
I
OL
(mA)
2
I
(mA)
Min (V)
Max (V)
Min (V)
Max (V)
LVCMOS 3.3
-0.3
0.8
2.0
5.5
0.4
2.4
20, 16, 12,
8, 5.33, 4
0.1
4
0.1
16, 12, 8,
5.33, 4
0.1
8
12, 5.33, 4
0.1
1.5
1.5
8
16
7.6
15.2
8
8
8
24
48
36
-20, -16, -12,
-8, -5.33, -4
-0.1
-4
-0.1
-16, -12, -8,
-5.33, -4
-0.1
-8
-12, -5.33, -4
-0.1
-0.5
-0.5
-8
-16
-7.6
-15.2
-8
-8
-8
-8
-8
n/a
0.2
0.4
0.2
V
CCO
- 0.2
2.4
V
CCO
- 0.2
LVTTL
-0.3
0.8
2.0
5.5
LVCMOS 2.5
-0.3
0.7
1.7
3.6
0.4
V
CCO
- 0.4
0.2
0.4
0.4
0.2
V
CCO
- 0.2
V
CCO
- 0.4
V
CCO
-0.4
V
CCO
- 0.2
0.9 V
CCO
0.9 V
CCO
V
CCO
- 1.1
V
CCO
- 0.9
V
CCO
- 0.62
V
CCO
- 0.43
V
REF
+ 0.4
V
REF
+ 0.4
V
CCO
- 0.4
V
CCO
- 0.4
V
CCO
- 0.4
n/a
LVCMOS 1.8
1, 3
-0.3
0.68
1.07
3.6
LVCMOS 1.8
3
-0.3
0.68
1.07
3.6
PCI 3.3
4
AGP-1X
4
SSTL3 class I
SSTL3 class II
SSTL2 class I
SSTL2 class II
CTT 3.3
CTT 2.5
HSTL class I
HSTL class III
HSTL class IV
GTL+
1. Software default setting.
2. The average DC current drawn by I/Os between adjacent bank GND connections, or between the last GND in an I/O bank and the end of
the I/O bank, as shown in the logic signals connection table, shall not exceed n*8mA. Where n is the number of I/Os between bank GND
connections or between the last GND in a bank and the end of a bank.
3. For 1.8V devices (ispXPLD 5000MC) these speci
fi
cations are V
IL
= 0.35 * V
CC
and V
IH
= 0.65 * V
CC.
4. For 1.8V devices (ispXPLD 5000MC) these speci
fi
cations are V
IL
= 0.3 * V
CC
* 3.3/1.8, V
IH
= 0.5 * V
CC
* 3.3/1.8.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
1.08
1.08
1.5
1.5
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
0.1 V
CCO
0.1 V
CCO
0.7
0.5
0.54
0.35
V
REF
- 0.4
V
REF
- 0.4
0.4
0.4
0.4
0.6
V
REF
- 0.2
V
REF
- 0.2
V
REF
- 0.18 V
REF
+ 0.18
V
REF
- 0.18 V
REF
+ 0.18
V
REF
- 0.2
V
REF
- 0.3
V
REF
- 0.1
V
REF
- 0.2
V
REF
- 0.3
V
REF
- 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.2
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參數(shù)描述
LC5512MC-45F256I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-45F484C 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5512MC-45F484I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-45F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MC-45F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family