- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19711 > LC5512MV-45Q208C (Lattice Semiconductor Corporation)IC XPLD 512MC 4.5NS 208PQFP PDF資料下載
參數(shù)資料
| 型號： | LC5512MV-45Q208C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 5/99頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XPLD 512MC 4.5NS 208PQFP |
| 標準包裝： | 24 |
| 系列： | ispXPLD® 5000MV |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 4.5ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 512 |
| 輸入/輸出數(shù)： | 149 |
| 工作溫度： | 0°C ~ 90°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
9
Table 4. MFB Memory Configuration
Input and Output
The data input and control signals to a MFB in memory mode are generated from inputs from the routing. Data sig-
nals are only available in the true non-inverted format. True or complemented versions of the inputs are available
for generating the control signals. Data and flag outputs are fed from the MFB to the GRP and OSA. Unused inputs
and outputs are not accessible in memory mode.
ROM Operation
In each of the memory modes it is possible to specify the power-on state of each bit in the memory array. This
allows the memory to be used as ROM if desired.
Increased Depth And Width
Designs that require a memory depth or width that is greater than that support by a single MFB can be supported
by cascading multiple blocks. For dual port, single port, and pseudo dual port modes additional width is easily pro-
vided by sharing address lines. Additional depth is supported by multiplexing the RAM output. For FIFO and CAM
modes additional width is supported through the cascading of MFBs.
The Lattice design tools automatically combine blocks to support the memory size specified in the user’s design.
Bus Size Matching
All of the memory modes apart from CAM mode support different widths on each of the ports. The RAM bits are
mapped LSB word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of
words for each port varies this mapping scheme applies to each port.
Memory Mode
Max. Configuration
Size
1
Dual-port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 8
512 x 16
Single-port, Pseudo Dual Port, FIFO
16,384 x1
8,192 x 2
4,096 x 4
2,048 x 8
1,024 x 16
512 x 32
CAM
128 x 48
1. Smaller configurations are possible.
SELECT
DEVICES
DISCONTINUED
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-BTM-CY-F1 | CONVERTER MOD DC/DC 10V 50W |
| VE-BT1-CY-F4 | CONVERTER MOD DC/DC 12V 50W |
| LC5512MV-75FN484I | IC CPLD 512MACROCELLS 484FPBGA |
| VE-BT1-CY-F2 | CONVERTER MOD DC/DC 12V 50W |
| VE-BT1-CY-F1 | CONVERTER MOD DC/DC 12V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC5512MV-45Q208I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MV-45Q256C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MV-45Q256I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MV-45Q484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5512MV-45Q484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。