fMAX (RAM) 5 Clock Fre" />
參數(shù)資料
型號: LC5512MV-75QN208I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 28/99頁
文件大小: 0K
描述: IC CPLD 512MACROCELLS 208PQFP
標(biāo)準(zhǔn)包裝: 1
系列: ispXPLD® 5000MV
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 16
宏單元數(shù): 512
輸入/輸出數(shù): 149
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
包裝: 托盤
其它名稱: 220-2620
LC5512MV-75QN208I-ND
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
30
fMAX (RAM)
5
Clock Frequency to RAM in:
Single Port Mode
155
155
155
155
93
MHz
Dual Port Mode
155
155
155
155
93
MHz
Pseudo Dual Port Mode
180
180
160
160
106
MHz
fMAX (FIFO)
5
Clock Frequency to FIFO
225
220
210
210
132
MHz
tPWR_ON
Power-on Time
200
200
200
200
200
s
Timing v.1.8
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate timing for other standards.
2. Measured using standard switching circuit, global routing loading of 1, worst case PTSA loading and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
5. CAM, FIFO, RAM fMAX specification used shared PT Clk.
ispXPLD 5000MX Family External Switching Characteristics (Continued)
1, 2, 3
Over Recommended Operating Conditions
Parameter
Description
-4
-45
-5
-52
-75
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
SELECT
DEVICES
DISCONTINUED
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