參數(shù)資料
型號(hào)： LC5768MC-75F484C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
中文描述： EE PLD, 9.5 ns, PBGA484
封裝： FPBGA-484
文件頁(yè)數(shù)： 2/92頁(yè)
文件大小： 378K
代理商： LC5768MC-75F484C
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
2
Figure 1. ispXPLD 5000MX Block Diagram
Introduction
The ispXPLD 5000MX family represents a new class of device, referred to as the eXpanded Programmable Logic
Devices (XPLDs). These devices extend the capability of Lattice’s popular SuperWIDE ispMACH 5000 architecture
by providing
fl
exible memory capability. The family supports single- or dual-port SRAM, FIFO, and ternary CAM
operation. Extra logic has also been included to allow ef
fi
cient implementation of arithmetic functions. In addition,
sysCLOCK PLLs and sysIO interfaces provide support for the system-level needs of designers.
The devices provide designers with a convenient one-chip solution that provides logic availability at boot-up, design
security, and extreme recon
fi
gurability. The use of advanced process technology provides industry-leading perfor-
mance with combinatorial propagation delay as low as 4.0ns, 2.8ns clock-to-out delay, 2.2ns set-up time, and oper-
ating frequency up to 300MHz. This performance is coupled with low static and dynamic power consumption. The
ispXPLD 5000MX architecture provides predictable deterministic timing.
The availability of 3.3, 2.5 and 1.8V versions of these devices along with the
fl
exibility of the sysIO interface helps
users meet the challenge of today’s mixed voltage designs. Inputs can be safely driven up to 5.5V when an I/O
bank is con
fi
gured for 3.3V operation, making this family 5V tolerant. Boundary scan testability further eases inte-
gration into today’s complex systems. A variety of density and package options increase the likelihood of a good t
for a particular application. Table 1 shows the members of the ispXPLD 5000MX family.
Architecture
The ispXPLD 5000MX devices consist of Multi-Function Blocks (MFBs) interconnected with a Global Routing Pool.
Signals enter and leave the device via one of four sysIO banks. Figure 1 shows the block diagram of the ispXPLD
ISP Port
Global
Routing
Pool
(GRP)
sysCLOCK
PLL 0
sysCLOCK
PLL 1
sysIO
Bank 0
MFB
MFB
MFB
MFB
V
CCO3
V
REF3
V
C
V
REF2
V
CCO2
GCLCK3
GCLK2
RESET
GOE0
GOE1
T
G
T
T
T
P
O
sysIO
Bank 1
sysIO
Bank 3
sysIO
Bank 2
MFB
MFB
MFB
MFB
O
O
O
V
CCO0
V
REF0
V
CCO1
V
CCP
V
REF1
GCLCK0
GNDP
GCLK1
Optional
sysCONFIG
Interface
V
C
相關(guān)PDF資料
PDF描述
LC801 SILICON GATE ENHANCEMENT MODE RF POWER LDMOS TRANSISTOR
LC821 SILICON GATE ENHANCEMENT MODE RF POWER LDMOS TRANSISTOR
LCAS6-10-L VI CHIP Evaluation Board
LCAS6-10-L-EB VI CHIP Evaluation Board
LCBG10P Bidirectional 3.3 V I/O Transceiver for SCSI-2, SCSI-3, and SCSI-3 Fast-20 Buses( 3.3 V 雙向I/O收發(fā)器（適用于SCSI-2,SCSI-3,和SCSI-3 Fast-20 總線）)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC5768MC-75F484I 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5768MC-75F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5768MC-75F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5768MC-75FN208C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5768MC-75FN208I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*