參數(shù)資料
型號(hào)： LC5768MC-75F484C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
中文描述： EE PLD, 9.5 ns, PBGA484
封裝： FPBGA-484
文件頁(yè)數(shù)： 31/92頁(yè)
文件大?。?/td> 378K
代理商： LC5768MC-75F484C
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
31
Timing Model
The task of determining timing in a ispXPLD 5000MX device is relatively simple. The timing model show in
Figure 20 shows the speci
fi
c delay paths. Once the implementation of a given function is determined either con-
ceptually or from the software report
fi
le, the delay path of a function can easily be determined from the timing
model. The Lattice design tools report the timing delays based on the same timing model. Note that internal timing
parameters are for reference only, and are not tested. The external timing parameters are tested and guaranteed
for every device.
Figure 20. ispXPLD 5000MX Timing Model Diagram
MC Reg
.
t
BUF
t
IOO
t
EN
t
DIS
OUT
DATA
C.E.
S/R
Q
t
PTCLK
t
BCLK
IN
t
GCLK _IN
IOI
GCLK
From Feedback
RST
OE
t
INREG
t
INDIO
Memory
Functions
t
PDi
t
PTSR
t
BSR
t
ORP
t
PTOE
t
SPTOE
t
GPTOE
t
IN
t
IOI
t
GOE
t
IOI
t
RST
t
IOI
t
PDb
CLK, CE and Reset Only
3
t
PLL _DELAY
t
PLL _SEC_DELAY
SUM
t
CICOMFB
t
CICOMC
t
EXP
t
PTSA
t
FBK
CASC
t
ROUTE
t
ROUTEMF
t
t
BLA
Some paths not available in memory
mode. Refer to timing tables for details.
Path only available for
FIFO Flags
t
GCLK
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