參數(shù)資料
型號(hào): LC72134M
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24
封裝: MFP-24
文件頁數(shù): 6/27頁
文件大小: 463K
代理商: LC72134M
No. 5814-14/27
LC72134M
No.
Control block/data
Description
Related data
1
I/O port data
12, I1
Data latched from the IFIN2/I1 input port (when L/I1 is 0) and the I/O port IO2 pin. The I2 data reflects the
pin state regardless of the I/O port mode (input or output). The data is latched at the point the circuit enters
data output mode (OUT mode).
The data is latched at the point the circuit enters data output mode (OUT mode).
I1
← IFIN2/I1 pin state
H : 1
I2
← The IO2 pin state
L : 0
L/I1
IOC2
Structure of the DO Output Data (serial data output)
OUT mode
DO Output Data
2
PLL unlocked state
data
UL
Indicates the state of the unlocked state detection circuit.
UL
← 0: When the PLL is unlocked.
UL
← 1: When the PLL is locked or in the detection disabled mode.
UL0, UL1
ULa, ULb
3
IF counter binary
data
C19 to C0
Indicates the value of the IF counter (20-bit binary counter).
C19
← MSB of the binary counter
C0
← LSB of the binary counter
CTE
GT0
GT1
4
IF counter selection
data
LCT
Data that reflects the LCTS bit in the serial input data. The LCT output data allows applications to verify the
IF counter input pin selection (IFIN1 or IFIN2).
LCT = 0: IFIN1 selected.
LCT = 1: IFIN2/I1 selected.
LCTS
Serial Data Input (IN1/IN2/IN3) tSU, tHD, tEL, tES, tEH ≥ 0.75 s tLC < 0.75 s
CL: Normal (high)
相關(guān)PDF資料
PDF描述
LC72135M PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20
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