參數(shù)資料
型號: LC72714
廠商: Sanyo Electric Co.,Ltd.
英文描述: Mobile FM Multiplex Broadcast IC with On-Chip VICS Decoder
中文描述: 多重移動調(diào)頻廣播集成電路片VICS解碼器
文件頁數(shù): 19/29頁
文件大?。?/td> 232K
代理商: LC72714
CPU Connection Example <Parallel Interface>
This section presents examples of the connection of this IC to a CPU.
Note that care is required with respect to read timing, since the time required to read a register, and the time required to
read a post-correction data packet (22 bytes) are different.
Normal connection
When hardware waits are applied to the
CPU, the wait time (RDY width)
requires care.
BUSWD = low: 8 bits
BUSWD = high: 16 bits
No. 6871-19/29
LC72714W
LC72714W
CPU
D0 to D7
(D0 to D15)
PORT1
RST
SP
IOCNT2
BUSWD
IOCNT1
WAIT
INT
CS
RD
WR
A0 to A3
WR
RD
CS
INT
RDY
DACK
DREQ
BUS-Width
8 bits
DMA transfer mode
I/O read/write operations are used for
the normal register read and write
operations. However, programmable
wait states may need to be inserted,
depending on the execution speeds.
DMA processing is only used for
readout of post-correction data.
Applications can select whether RD or
DACK is used as the DMA read control
signal by setting a register.
The default is to use the RD signal.
The data bus width in DMA mode is
always 8 bits.
CPU DMA mode setting example (For
reference only)
SH Series: Transfer type: 2-cycle
transfer
Transfer mode: Single
transfer mode
V Series:
Address mode: Dual
address mode
Bus mode: Cycle
stealing mode
The source side (the FM multiplex IC)
address is fixed at 0.
LC72714W
CPU
D0 to D7
PORT1
RST
IOCNT2
IOCNT1
DACK
DREQ
INT
CS
RD
WR
A0 to A3
WR
RD
CS
INT
RDY
DREQ
DACK
SP
BUSWD
BUS-Width
8 bits
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參數(shù)描述
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