參數(shù)資料
型號: LFEC6E-4TN144I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 103/163頁
文件大?。?/td> 0K
描述: IC FPGA 6.1KLUTS 97I/O 144-TQFP
標準包裝: 60
系列: EC
邏輯元件/單元數(shù): 6100
RAM 位總計: 94208
輸入/輸出數(shù): 97
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 144-LQFP
供應商設備封裝: 144-TQFP(20x20)
3-8
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Differential HSTL and SSTL
Differential HSTL and SSTL outputs are implemented as a pair of complementary single-ended outputs. All allow-
able single-ended output classes (class I and class II) are supported in this mode.
LVDS25E
The top and bottom side of LatticeECP/EC devices support LVDS outputs via emulated complementary LVCMOS
outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in
Figure 3-1 is one possible solution for point-to-point signals.
Figure 3-1. LVDS25E Output Termination Example
Table 3-1. LVDS25E DC Conditions
Parameter
Description
Typical
Units
VOH
Output high voltage
1.42
V
VOL
Output low voltage
1.08
V
VOD
Output differential voltage
0.35
V
VCM
Output common mode voltage
1.25
V
ZBACK
Back impedance
100
+
-
Bourns
CAT16-LV4F12
RS=165 ohms
(±1%)
RS=165 ohms
(±1%)
RD = 140 ohms
(±1%)
RD = 100 ohms
(±1%)
OFF-chip
Transmission line, Zo = 100 ohm differential
VCCIO = 2.5V (±5%)
ON-chip
OFF-chip
ON-chip
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