參數(shù)資料
型號: LFEC6E-4TN144I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 96/163頁
文件大?。?/td> 0K
描述: IC FPGA 6.1KLUTS 97I/O 144-TQFP
標(biāo)準(zhǔn)包裝: 60
系列: EC
邏輯元件/單元數(shù): 6100
RAM 位總計: 94208
輸入/輸出數(shù): 97
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
3-2
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
IIL, IIH
1
Input or I/O Leakage
0 VIN (VCCIO - 0.2V)
10
A
IIH
1, 3
Input or I/O High Leakage
(VCCIO - 0.2V) VIH 3.6V
40
A
IPU
I/O Active Pull-up Current
0 VIN 0.7 VCCIO
-30
-150
A
IPD
I/O Active Pull-down Current
VIL (MAX) VIN VIH (MAX)
30
150
A
IBHLS
Bus Hold Low sustaining current
VIN = VIL (MAX)
30
A
IBHHS
Bus Hold High sustaining current
VIN = 0.7VCCIO
-30
A
IBHLO
Bus Hold Low Overdrive current
0 VIN VIH (MAX)
150
A
IBHLH
Bus Hold High Overdrive current
0 VIN VIH (MAX)
-150
A
VBHT
Bus Hold trip Points
0 VIN VIH (MAX)
VIL (MAX)
VIH (MIN)
V
C1
I/O Capacitance
2
VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
VCC = 1.2V, VIO = 0 to VIH (MAX)
—8
pf
C2
Dedicated Input Capacitance
2
VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,
VCC = 1.2V, VIO = 0 to VIH (MAX)
—6
pf
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. TA 25
oC, f = 1.0MHz
3. For top and bottom general purpose I/O pins, when VIH is higher than VCCIO, a transient current typically of 30ns in duration or less with a
peak current of 6mA can occur on the high-to-low transition. For left and right I/O banks, VIH must be less than or equal to VCCIO.
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