參數(shù)資料
型號(hào): LFEC6E-4TN144I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 69/163頁
文件大?。?/td> 0K
描述: IC FPGA 6.1KLUTS 97I/O 144-TQFP
標(biāo)準(zhǔn)包裝: 60
系列: EC
邏輯元件/單元數(shù): 6100
RAM 位總計(jì): 94208
輸入/輸出數(shù): 97
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
September 2012
Data Sheet
2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
6-1
Further Info_01.4
For Further Information
A variety of technical notes for the LatticeECP/EC family are available on the Lattice web site at www.latticesemi.com.
LatticeECP/EC sysIO Usage Guide (TN1056)
LatticeECP/EC sysCLOCK PLL Design and Usage Guide (TN1049)
Memory Usage Guide for LatticeECP/EC Devices (TN1051)
LatticeECP/EC DDR Usage Guide (TN1050)
Power Estimation and Management for LatticeECP/EC and LatticeXP Devices (TN1052)
LatticeECP-DSP sysDSP Usage Guide (TN1057)
LatticeECP/EC sysCONFIG Usage Guide (TN1053)
IEEE 1149.1 Boundary Scan Testability in Lattice Devices
For further information about interface standards refer to the following web sites:
JEDEC Standards (LVTTL, LVCMOS, SSTL, HSTL): www.jedec.org
PCI: ww.pcisig.com
LatticeECP/EC Family Data Sheet
Supplemental Information
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