參數(shù)資料
型號: LFEC6E-4TN144I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 105/163頁
文件大?。?/td> 0K
描述: IC FPGA 6.1KLUTS 97I/O 144-TQFP
標準包裝: 60
系列: EC
邏輯元件/單元數(shù): 6100
RAM 位總計: 94208
輸入/輸出數(shù): 97
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 144-LQFP
供應商設備封裝: 144-TQFP(20x20)
3-10
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LVPECL
The LatticeECP/EC devices support differential LVPECL standard. This standard is emulated using complemen-
tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard
is supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for
point-to-point signals.
Figure 3-3. Differential LVPECL
Table 3-3. LVPECL DC Conditions1
Over Recommended Operating Conditions
For further information about LVPECL, BLVDS and other differential interfaces please see the list of technical infor-
mation at the end of this data sheet.
Parameter
Description
Typical
Units
ZOUT
Output impedance
100
ohm
RP
Driver parallel resistor
150
ohm
RT
Receiver termination
100
ohm
VOH
Output high voltage
2.03
V
VOL
Output low voltage
1.27
V
VOD
Output differential voltage
0.76
V
VCM
Output common mode voltage
1.65
V
ZBACK
Back impedance
85.7
ohm
IDC
DC output current
12.7
mA
1. For input buffer, see LVDS table.
Transmission line, Zo = 100 ohm differential
100 ohms
Off-chip
3.3V
+
-
~150 ohms
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