參數(shù)資料
型號: LFECP10E-4QN208C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 101/163頁
文件大?。?/td> 0K
描述: IC FPGA 10.2KLUTS 208PQFP
標準包裝: 24
系列: ECP
邏輯元件/單元數(shù): 10200
RAM 位總計: 282624
輸入/輸出數(shù): 147
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
3-6
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
sysI/O Single-Ended DC Electrical Characteristics
Input/Output
Standard
VIL
VIH
VOL Max.
(V)
VOH Min.
(V)
IOL
1
(mA)
IOH
1
(mA)
Min. (V)
Max. (V)
Min. (V)
Max. (V)
LVCMOS 3.3
-0.3
0.8
2.0
3.6
0.4
VCCIO - 0.4
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
0.2
VCCIO - 0.2
0.1
-0.1
LVTTL
-0.3
0.8
2.0
3.6
0.4
VCCIO - 0.4
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
0.2
VCCIO - 0.2
0.1
-0.1
LVCMOS 2.5
-0.3
0.7
1.7
3.6
0.4
VCCIO - 0.4
20, 16, 12,
8, 4
-20, -16, -12,
-8, -4
0.2
VCCIO - 0.2
0.1
-0.1
LVCMOS 1.8
-0.3
0.35VCCIO
0.65VCCIO
3.6
0.4
VCCIO - 0.4
16, 12, 8, 4
-16, -12, -8, -4
0.2
VCCIO - 0.2
0.1
-0.1
LVCMOS 1.5
-0.3
0.35VCCIO
0.65VCCIO
3.6
0.4
VCCIO - 0.4
8, 4
-8, -4
0.2
VCCIO - 0.2
0.1
-0.1
LVCMOS 1.2
-0.3
0.35VCC
0.65VCC
3.6
0.4
VCCIO - 0.4
6, 2
-6, -2
0.2
VCCIO - 0.2
0.1
-0.1
PCI
-0.3
0.3VCCIO
0.5VCCIO
3.6
0.1VCCIO
0.9VCCIO
1.5
-0.5
SSTL3 class I
-0.3
VREF - 0.2
VREF + 0.2
3.6
0.7
VCCIO - 1.1
8
-8
SSTL3 class II
-0.3
VREF - 0.2
VREF + 0.2
3.6
0.5
VCCIO - 0.9
16
-16
SSTL2 class I
-0.3
VREF - 0.18 VREF + 0.18
3.6
0.54
VCCIO - 0.62
7.6
-7.6
SSTL2 class II
-0.3
VREF - 0.18 VREF + 0.18
3.6
0.35
VCCIO - 0.43
15.2
-15.2
SSTL18 class I
-0.3
VREF - 0.125 VREF + 0.125
3.6
0.4
VCCIO - 0.4
6.7
-6.7
HSTL15 class I
-0.3
VREF - 0.1
VREF + 0.1
3.6
0.4
VCCIO - 0.4
8
-8
HSTL15 class III
-0.3
VREF - 0.1
VREF + 0.1
3.6
0.4
VCCIO - 0.4
24
-8
HSTL18 class I
-0.3
VREF - 0.1
VREF + 0.1
3.6
0.4
VCCIO - 0.4
9.6
-9.6
HSTL18 class II
-0.3
VREF - 0.1
VREF + 0.1
3.6
0.4
VCCIO - 0.4
16
-16
HSTL18 class III
-0.3
VREF - 0.1
VREF + 0.1
3.6
0.4
VCCIO - 0.4
24
-8
1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as
shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between bank GND connections or
between the last GND in a bank and the end of a bank.
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