參數(shù)資料
型號(hào): LFECP10E-4QN208C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 121/163頁
文件大小: 0K
描述: IC FPGA 10.2KLUTS 208PQFP
標(biāo)準(zhǔn)包裝: 24
系列: ECP
邏輯元件/單元數(shù): 10200
RAM 位總計(jì): 282624
輸入/輸出數(shù): 147
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
3-24
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
LatticeECP/EC sysCONFIG Port Timing Specifications
Over Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Units
sysCONFIG Byte Data Flow
tSUCBDI
Byte D[0:7] Setup Time to CCLK
7
ns
tHCBDI
Byte D[0:7] Hold Time to CCLK
1
ns
tCODO
Clock to Dout in Flowthrough Mode
12
ns
tSUCS
CS[0:1] Setup Time to CCLK
7
ns
tHCS
CS[0:1] Hold Time to CCLK
1
ns
tSUWD
Write Signal Setup Time to CCLK
7
ns
tHWD
Write Signal Hold Time to CCLK
1
ns
tDCB
CCLK to BUSY Delay Time
12
ns
tCORD
Clock to Out for Read Data
12
ns
sysCONFIG Byte Slave Clocking
tBSCH
Byte Slave Clock Minimum High Pulse
6
ns
tBSCL
Byte Slave Clock Minimum Low Pulse
9
ns
tBSCYC
Byte Slave Clock Cycle Time
15
ns
tSUSCDI
Din Setup time to CCLK Slave Mode
7
ns
tHSCDI
Din Hold Time to CCLK Slave Mode
1
ns
tCODO
Clock to Dout in Flowthrough Mode
12
ns
sysCONFIG Serial (Bit) Data Flow
tSUMCDI
Din Setup time to CCLK Master Mode
7
ns
tHMCDI
Din Hold Time to CCLK Master Mode
1
ns
sysCONFIG Serial Slave Clocking
tSSCH
Serial Slave Clock Minimum High Pulse
6
ns
tSSCL
Serial Slave Clock Minimum Low Pulse
6
ns
sysCONFIG POR, Initialization and Wake Up
tICFG
Minimum Vcc to INIT High
50
ms
tVMC
Time from tICFG to Valid Master Clock
2
us
tPRGMRJ
Program Pin Pulse Rejection
8
ns
tPRGM
PROGRAMN Low Time to Start Configuration
25
ns
tDINIT
INIT Low Time
1
ms
tDPPINIT
Delay Time from PROGRAMN Low to INIT Low
37
ns
tDINITD
Delay Time from PROGRAMN Low to DONE Low
37
ns
tIODISS
User I/O Disable from PROGRAMN Low
35
ns
tIOENSS
User I/O Enabled Time from CCLK Edge During Wake Up
Sequence
25
ns
tMWC
Additional Wake Master Clock Signals after Done Pin High
120
cycles
tSUCFG
CFG to INITN Setup Time
100
ns
tHCFG
CFG to INITN Hold Time
100
ns
sysCONFIG SPI Port
tCFGX
Init High to CCLK Low
80
ns
tCSSPI
Init High to CSSPIN Low
2
us
tCSCCLK
CCLK Low Before CSSPIN Low
0
-
ns
tSOCDO
CCLK Low to Output Valid
15
ns
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