Figure 2-5. Distributed Memory Primitives ROM Mode: The ROM mode uses the same principal as th" />
參數(shù)資料
型號: LFECP10E-4QN208C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 153/163頁
文件大?。?/td> 0K
描述: IC FPGA 10.2KLUTS 208PQFP
標準包裝: 24
系列: ECP
邏輯元件/單元數(shù): 10200
RAM 位總計: 282624
輸入/輸出數(shù): 147
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
2-6
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-5. Distributed Memory Primitives
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during configuration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
Table 2-4. PFU Modes of Operation
Logic
Ripple
RAM1
ROM
LUT 4x8 or
MUX 2x1 x 8
2-bit Add x 4
SPR16x2 x 4
DPR16x2 x 2
ROM16x1 x 8
LUT 5x4 or
MUX 4x1 x 4
2-bit Sub x 4
SPR16x4 x 2
DPR16x4 x 1
ROM16x2 x 4
LUT 6x 2 or
MUX 8x1 x 2
2-bit Counter x 4
SPR16x8 x 1
ROM16x4 x 2
LUT 7x1 or
MUX 16x1 x 1
2-bit Comp x 4
ROM16x8 x 1
1. These modes are not available in PFF blocks
DO1
DO0
DI0
DI1
AD0
AD1
AD2
AD3
WRE
CK
DO0
AD0
AD1
AD2
AD3
DPR16x2
SPR16x2
ROM16x1
RDO1
RDO0
DI0
DI1
WCK
WRE
WDO1
WDO0
WAD0
WAD1
WAD2
WAD3
RAD0
RAD1
RAD2
RAD3
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LFECP10E-4QN208I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10.2K LUTs 147 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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