參數(shù)資料
型號: LH28F320BFHE-PBTLZ2
廠商: Sharp Corporation
英文描述: 32M (x16) Flash Memory
中文描述: 32M的(x16)的快閃記憶體
文件頁數(shù): 23/36頁
文件大?。?/td> 689K
代理商: LH28F320BFHE-PBTLZ2
LHF32FD2 21
1.2.4 AC Characteristics - Read-Only Operations
(1)
NOTES:
1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.
2. Sampled, not 100% tested.
3. OE# may be delayed up to t
ELQV
t
GLQV
after the falling edge of CE# without impact to t
ELQV
.
4. Address setup time (t
AVEL
, t
AVGL
) is defined from the falling edge of CE# or OE# (whichever goes low last).
5. Address hold time (t
ELAX
, t
GLAX
) is defined from the falling edge of CE# or OE# (whichever goes low last).
6. Specifications t
AVEL
, t
AVGL
, t
ELAX
, t
GLAX
and t
EHEL
, t
GHGL
for read operations apply to only status register read
operations.
V
CC
=2.7V-3.6V, T
A
=-40
°
C to +85
°
C
Symbol
t
AVAV
t
AVQV
t
ELQV
t
APA
t
GLQV
t
PHQV
t
EHQZ
, t
GHQZ
t
ELQX
t
GLQX
t
OH
Parameter
Notes
Min.
Max.
Unit
Read Cycle Time
80
ns
Address to Output Delay
80
ns
CE# to Output Delay
3
80
ns
Page Address Access Time
35
ns
OE# to Output Delay
3
20
ns
RST# High to Output Delay
150
ns
CE# or OE# to Output in High Z, Whichever Occurs First
2
20
ns
CE# to Output in Low Z
2
0
ns
OE# to Output in Low Z
2
0
ns
Output Hold from First Occurring Address, CE# or OE# change
2
0
ns
t
AVEL
, t
AVGL
Address Setup to CE#, OE# Going Low
for Reading Status Register
Address Hold from CE#, OE# Going Low
for Reading Status Register
CE#, OE# Pulse Width High for Reading
Status Register
4, 6
10
ns
t
ELAX
, t
GLAX
5, 6
30
ns
t
EHEL
, t
GHGL
6
25
ns
Rev. 2.44
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