參數(shù)資料
型號: LH28F640SPHT-PTL12
廠商: Sharp Corporation
英文描述: 64Mbit (4Mbitx16/8Mbitx8) Page Flash Memory
中文描述: 64兆比特(4Mbitx16/8Mbitx8)頁閃存
文件頁數(shù): 11/45頁
文件大?。?/td> 1041K
代理商: LH28F640SPHT-PTL12
LHF64P01 9
Rev. 0.06
NOTES:
1. Refer to DC Characteristics. When V
PEN
V
PENLK
, memory contents can be read, but cannot be altered.
2. X can be V
IL
or V
IH
for control pins and addresses, and V
PENLK
or V
PENH
for V
PEN
.
Refer to DC Characteristics for V
PENLK
and V
PENH
voltages.
3. Refer to Table 2 to determine whether the device is selected or de-selected depending on the state of CE
0
, CE
1
and CE
2
.
4. DQ refers to DQ
15
-DQ
0
in word mode (BYTE#=V
IH
:
×
16 bit) and DQ
7
-DQ
0
in byte mode (BYTE#=V
IL
:
×
8 bit).
5. RP# at GND±0.2V ensures the lowest power consumption.
6. Command writes involving block erase, (page buffer) program, block lock configuration or OTP program are reliably
executed when V
PEN
=V
PENH
and V
CC
=2.7V-3.6V.
7. Refer to Table 5 for valid D
IN
during a write operation.
8. Never hold OE# low and WE# low at the same timing.
9. Refer to Appendix of LH28F640SP series for more information about query code.
10. STS is V
OL
when the WSM (Write State Machine) is executing internal block erase, (page buffer) program or OTP
program algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with program and page
buffer program inactive), (page buffer) program suspend mode, or reset mode.
Table 4. Bus Operation
(1, 2)
Mode
Notes
RP#
CE
0,1,2
(3)
OE#
WE#
Address
V
PEN
DQ
(4)
STS
(10)
Read Array
8
V
IH
V
IH
V
IH
V
IL
Enabled
V
IL
V
IH
V
IH
V
IH
X
X
D
OUT
X
Output Disable
Enabled
X
X
High Z
X
Standby
Disabled
X
X
X
X
High Z
X
Reset
5
X
X
X
X
X
High Z
High Z
Read Identifier
Codes/OTP
Read Query
8
V
IH
Enabled
V
IL
V
IH
Refer to
Table 3
See
Appendix
X
Refer to
Table 3
See
Appendix
D
IN
X
8,9
V
IH
Enabled
V
IL
V
IH
X
X
Write
6,7,8
V
IH
Enabled
V
IH
V
IL
X
X
X
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