參數(shù)資料
型號： LH28F640SPHT-PTL12
廠商： Sharp Corporation
英文描述： 64Mbit (4Mbitx16/8Mbitx8) Page Flash Memory
中文描述： 64兆比特（4Mbitx16/8Mbitx8）頁閃存
文件頁數(shù)： 6/45頁
文件大?。?/td> 1041K
代理商： LH28F640SPHT-PTL12
LHF64P01 4
Table 1. Pin Descriptions
Symbol
Type
Name and Function
A
0
INPUT
ADDRESS INPUTS: Lowest address input in byte mode (BYTE#=V
IL
:
×
8 bit).
Address is internally latched during an erase or a program cycle. This pin is not used in
word mode (BYTE#=V
IH
:
×
16 bit)
ADDRESS INPUTS: Inputs for addresses during read, erase and program operations.
Addresses are internally latched during an erase or a program cycle.
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code,
identifier code reads. Data pins float to high-impedance (High Z) when the chip or
outputs are deselected. Data is internally latched during an erase or program cycle.
DQ
15
-DQ
8
pins are not used in byte mode (BYTE#=V
IL
:
×
8 bit).
CHIP ENABLE: Activates the device
’
s control logic, input buffers, decoders and sense
amplifiers. When the device is de-selected, power consumption reduces to standby
levels. Refer to Table 2 to determine whether the device is selected or de-selected
depending on the state of CE
0
, CE
1
and CE
2
.
RESET: When low (V
IL
), RP# resets internal automation and inhibits erase and program
operations, which provides data protection. RP#-high (V
IH
) enables normal operation.
After power-up or reset mode, the device is automatically set to read array mode.
RP# must be low during power-up/down.
OUTPUT ENABLE: Gates the device
’
s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the first edge of CE
0
, CE
1
or CE
2
that disables the device or the rising edge of
WE# (whichever occurs first).
STATUS: Indicates the status of the internal WSM (Write State Machine). When
configured in level mode (default mode), STS acts as a RY/BY# pin (STS is V
OL
when
the WSM is executing internal erase or program algorithms). When configured in one of
its pulse modes, STS can pulse to indicate erase/program completion. Refer to Table 9
for STS configuration.
BYTE ENABLE: BYTE# V
IL
places the device in byte mode (
×
8). In this mode, DQ
15
-
DQ
8
is floated (High Z) and A
0
is the lowest address input. BYTE# V
IH
places the
device in word mode (
×
16) and A
1
is the lowest address input.
MONITORING POWER SUPPLY VOLTAGE: V
PEN
is not used for power supply pin.
With V
PEN
≤
V
PENLK
, block erase, (page buffer) program, block lock configuration and
OTP program cannot be executed and should not be attempted.
DEVICE POWER SUPPLY (2.7V-3.6V): With V
CC
≤
V
LKO
, all write attempts to the
flash memory are inhibited. Device operations at invalid V
CC
voltage (refer to DC
Characteristics) produce spurious results and should not be attempted.
INPUT/OUTPUT POWER SUPPLY (2.7V-3.6V): Power supply for all input/output
pins.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internally connected; it may be driven or floated.
A
22
-A
1
INPUT
DQ
15
-DQ
0
INPUT/
OUTPUT
CE
0
,
CE
1
,
CE
2
INPUT
RP#
INPUT
OE#
INPUT
WE#
INPUT
STS
OPEN DRAIN
OUTPUT
BYTE#
INPUT
V
PEN
INPUT
V
CC
SUPPLY
V
CCQ
SUPPLY
GND
NC
SUPPLY
Rev. 0.06
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