參數(shù)資料
型號: LH5PV16256
廠商: Sharp Corporation
英文描述: CMOS 4M (256K x 16) Pseudo-Static RAM
中文描述: 的CMOS 4分(256K × 16),偽靜態(tài)存儲器
文件頁數(shù): 3/14頁
文件大?。?/td> 116K
代理商: LH5PV16256
TRUTH TABLE
CE
CS
RFSH
OE
UWE
LWE
MODE
I/O
0 - 7
I/O8 - 15
L
H
H
L
H
H
Word Read
Output data
Output data
L
H
H
X
H
L
Write
Lower byte write
Input data
Don’t care
L
H
Upper byte write
Don’t care
Input data
L
L
Word write
Input data
Input data
H
H
Invalid
High-Z
High-Z
H
X
L
X
X
X
Auto refresh
High-Z
High-Z
L
L
H
X
X
X
CS standby
High-Z
High-Z
H
X
H
X
X
X
Standby
High-Z
High-Z
NOTES:
H = High
L = Low
X = Don’t care
REQUIREMENTS
2WE control
Please do not separate the UWE and LWE operation timing intentionally in the same write cycles. Each of the
UWE/LWE should satisfy the timing specifications individually.
Refresh after self-refresh or data retention mode
If address refresh is used during normal read/write cycles, the first address refresh must be executed within
15
μ
s after self-refresh or data retention mode ends and the address refresh must be executed continuously for
2,048 refresh cycles.
If distributed auto-refresh is used during normal read/write cycles, the first auto-refresh must be executed within
15
μ
s after self-refresh or data retention mode ends.
If burst auto-refresh is used during normal read/write cycles, the first auto-refresh must be executed within
15
μ
s after self-refresh or data retention mode ends, and the auto-refresh must be executed continuously for
2,048 refresh cycles.
Bypass capacitor for power supply noise reduction
Because a PSRAM operates dynamically like a DRAM, it is recommended to put bypass capacitors between V
CC
and GND to absorb power supply noise due to the peak current.
CMOS 4M (256
×
16) Pseudo-Static RAM
LH5PV16256
3
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